#[repr(u64)]
pub enum Value {
NonCacheable,
Cacheable,
}
Expand description
Cacheability control, for data accesses.
0 All data access to Normal memory from EL0 and EL1, and all Normal memory accesses to the EL1&0 stage 1 translation tables, are Non-cacheable for all levels of data and unified cache.
1 This control has no effect on the Cacheability of:
- Data access to Normal memory from EL0 and EL1.
- Normal memory accesses to the EL1&0 stage 1 translation tables.
When the value of the HCR_EL2.DC bit is 1, the PE ignores SCLTR.C. This means that Non-secure EL0 and Non-secure EL1 data accesses to Normal memory are Cacheable.
When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on the PE.
When this register has an architecturally-defined reset value, this field resets to 0.
Variants
NonCacheable
Cacheable
Trait Implementations
sourceimpl TryFromValue<u64> for Value
impl TryFromValue<u64> for Value
impl Copy for Value
impl Eq for Value
impl StructuralEq for Value
impl StructuralPartialEq for Value
Auto Trait Implementations
impl RefUnwindSafe for Value
impl Send for Value
impl Sync for Value
impl Unpin for Value
impl UnwindSafe for Value
Blanket Implementations
sourceimpl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
const: unstable · sourcefn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more