Enum cortex_a::registers::SCTLR_EL1::WXN::Value

#[repr(u64)]
pub enum Value {
    Disable,
    Enable,
}

Write permission implies XN (Execute-never). For the EL1&0 translation regime, this bit can force all memory regions that are writable to be treated as XN.

0 This control has no effect on memory access permissions.

1 Any region that is writable in the EL1&0 translation regime is forced to XN for accesses from software executing at EL1 or EL0.

The WXN bit is permitted to be cached in a TLB.

When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on the PE.

Variants

Disable

Enable

Trait Implementations

impl TryFromValue<u64> for Value

type EnumType = Value

fn try_from(v: u64) -> Option<Self::EnumType>