Module cortex_a::registers::SCTLR_EL2::M[−][src]

Expand description

MMU enable for EL2 or EL2&0 stage 1 address translation. Possible values of this bit are:

0 - When HCR_EL2.{E2H, TGE} != {1, 1}, EL2 stage 1 address translation disabled.

  • When HCR_EL2.{E2H, TGE} == {1, 1}, EL2&0 stage 1 address translation disabled.
  • See the SCTLR_EL2.I field for the behavior of instruction accesses to Normal memory.

1 - When HCR_EL2.{E2H, TGE} != {1, 1}, EL2 stage 1 address translation enabled.

  • When HCR_EL2.{E2H, TGE} == {1, 1}, EL2&0 stage 1 address translation enabled.

On a Warm reset, in a system where the PE resets into EL2, this field resets to 0.

Enums

Value

MMU enable for EL2 or EL2&0 stage 1 address translation. Possible values of this bit are:

Constants

CLEAR
Disable
Enable
SET