Enum cortex_a::registers::SCTLR_EL1::UCI::Value [−][src]
#[repr(u64)]
pub enum Value {
Trap,
DontTrap,
}Expand description
Traps EL0 execution of cache maintenance instructions to EL1, from AArch64 state only.
0 Any attempt to execute a DC CVAU, DC CIVAC, DC CVAC, DC CVAP, or IC IVAU instruction at EL0 using AArch64 is trapped to EL1. 1 This control does not cause any instructions to be trapped.
When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on execution at EL0.
If the Point of Coherency is before any level of data cache, it is IMPLEMENTATION DEFINED whether the execution of any data or unified cache clean, or clean and invalidate instruction that operates by VA to the point of coherency can be trapped when the value of this control is 1.
If the Point of Unification is before any level of data cache, it is IMPLEMENTATION DEFINED whether the execution of any data or unified cache clean by VA to the point of unification instruction can be trapped when the value of this control is 1.
If the Point of Unification is before any level of instruction cache, it is IMPLEMENTATION DEFINED whether the execution of any instruction cache invalidate by VA to the point of unification instruction can be trapped when the value of this control is 1.