[−]Module cortex_a::regs::HCR_EL2
Modules
DC | Default Cacheability. |
RW | Execution state control for lower Exception levels: |
SWIO | Set/Way Invalidation Override. Causes Non-secure EL1 execution of the data cache invalidate by set/way instructions to perform a data cache clean and invalidate by set/way: |
Structs
Register |
Constants
DC | |
RW | |
SWIO |