corstone300_pac/sysinfo/
sys_config0.rs

1// Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
2//
3// SPDX-License-Identifier: MIT
4
5#[doc = "Register `SYS_CONFIG0` reader"]
6pub struct R(crate::R<SYS_CONFIG0_SPEC>);
7impl core::ops::Deref for R {
8    type Target = crate::R<SYS_CONFIG0_SPEC>;
9    #[inline(always)]
10    fn deref(&self) -> &Self::Target {
11        &self.0
12    }
13}
14impl From<crate::R<SYS_CONFIG0_SPEC>> for R {
15    #[inline(always)]
16    fn from(reader: crate::R<SYS_CONFIG0_SPEC>) -> Self {
17        R(reader)
18    }
19}
20#[doc = "Field `NUM_VM_BANK` reader - Number of Volatile Memory Banks."]
21pub type NUM_VM_BANK_R = crate::FieldReader<u8, u8>;
22#[doc = "Field `VM_ADDR_WIDTH` reader - Volatile Memory Bank Address Width, where the size of each bank is equal to 2VM_ADDR_WIDTH bytes."]
23pub type VM_ADDR_WIDTH_R = crate::FieldReader<u8, u8>;
24#[doc = "Field `HAS_CRYPTO` reader - CryptoCell Included."]
25pub type HAS_CRYPTO_R = crate::BitReader<HAS_CRYPTO_A>;
26#[doc = "CryptoCell Included.\n\nValue on reset: 0"]
27#[derive(Clone, Copy, Debug, PartialEq, Eq)]
28pub enum HAS_CRYPTO_A {
29    #[doc = "0: CryptoCell Not Included"]
30    NO = 0,
31    #[doc = "1: CryptoCell Included"]
32    YES = 1,
33}
34impl From<HAS_CRYPTO_A> for bool {
35    #[inline(always)]
36    fn from(variant: HAS_CRYPTO_A) -> Self {
37        variant as u8 != 0
38    }
39}
40impl HAS_CRYPTO_R {
41    #[doc = "Get enumerated values variant"]
42    #[inline(always)]
43    pub fn variant(&self) -> HAS_CRYPTO_A {
44        match self.bits {
45            false => HAS_CRYPTO_A::NO,
46            true => HAS_CRYPTO_A::YES,
47        }
48    }
49    #[doc = "Checks if the value of the field is `NO`"]
50    #[inline(always)]
51    pub fn is_no(&self) -> bool {
52        *self == HAS_CRYPTO_A::NO
53    }
54    #[doc = "Checks if the value of the field is `YES`"]
55    #[inline(always)]
56    pub fn is_yes(&self) -> bool {
57        *self == HAS_CRYPTO_A::YES
58    }
59}
60#[doc = "Field `HAS_CSS` reader - Include CoreSight SoC-600 based Debug infrastructure."]
61pub type HAS_CSS_R = crate::BitReader<HAS_CSS_A>;
62#[doc = "Include CoreSight SoC-600 based Debug infrastructure.\n\nValue on reset: 0"]
63#[derive(Clone, Copy, Debug, PartialEq, Eq)]
64pub enum HAS_CSS_A {
65    #[doc = "0: Not included."]
66    NO = 0,
67    #[doc = "1: Included."]
68    YES = 1,
69}
70impl From<HAS_CSS_A> for bool {
71    #[inline(always)]
72    fn from(variant: HAS_CSS_A) -> Self {
73        variant as u8 != 0
74    }
75}
76impl HAS_CSS_R {
77    #[doc = "Get enumerated values variant"]
78    #[inline(always)]
79    pub fn variant(&self) -> HAS_CSS_A {
80        match self.bits {
81            false => HAS_CSS_A::NO,
82            true => HAS_CSS_A::YES,
83        }
84    }
85    #[doc = "Checks if the value of the field is `NO`"]
86    #[inline(always)]
87    pub fn is_no(&self) -> bool {
88        *self == HAS_CSS_A::NO
89    }
90    #[doc = "Checks if the value of the field is `YES`"]
91    #[inline(always)]
92    pub fn is_yes(&self) -> bool {
93        *self == HAS_CSS_A::YES
94    }
95}
96#[doc = "Field `PI_LEVEL` reader - Power Infrastructure Level"]
97pub type PI_LEVEL_R = crate::FieldReader<u8, PI_LEVEL_A>;
98#[doc = "Power Infrastructure Level\n\nValue on reset: 0"]
99#[derive(Clone, Copy, Debug, PartialEq, Eq)]
100#[repr(u8)]
101pub enum PI_LEVEL_A {
102    #[doc = "1: Intermediate Level"]
103    INTERMEDIATE_LEVEL = 1,
104}
105impl From<PI_LEVEL_A> for u8 {
106    #[inline(always)]
107    fn from(variant: PI_LEVEL_A) -> Self {
108        variant as _
109    }
110}
111impl PI_LEVEL_R {
112    #[doc = "Get enumerated values variant"]
113    #[inline(always)]
114    pub fn variant(&self) -> Option<PI_LEVEL_A> {
115        match self.bits {
116            1 => Some(PI_LEVEL_A::INTERMEDIATE_LEVEL),
117            _ => None,
118        }
119    }
120    #[doc = "Checks if the value of the field is `INTERMEDIATE_LEVEL`"]
121    #[inline(always)]
122    pub fn is_intermediate_level(&self) -> bool {
123        *self == PI_LEVEL_A::INTERMEDIATE_LEVEL
124    }
125}
126#[doc = "Field `CPU0_TYPE` reader - CPU 0 Core Type"]
127pub type CPU0_TYPE_R = crate::FieldReader<u8, CPU0_TYPE_A>;
128#[doc = "CPU 0 Core Type\n\nValue on reset: 0"]
129#[derive(Clone, Copy, Debug, PartialEq, Eq)]
130#[repr(u8)]
131pub enum CPU0_TYPE_A {
132    #[doc = "3: Cortex-M55"]
133    CORTEX_M55 = 3,
134}
135impl From<CPU0_TYPE_A> for u8 {
136    #[inline(always)]
137    fn from(variant: CPU0_TYPE_A) -> Self {
138        variant as _
139    }
140}
141impl CPU0_TYPE_R {
142    #[doc = "Get enumerated values variant"]
143    #[inline(always)]
144    pub fn variant(&self) -> Option<CPU0_TYPE_A> {
145        match self.bits {
146            3 => Some(CPU0_TYPE_A::CORTEX_M55),
147            _ => None,
148        }
149    }
150    #[doc = "Checks if the value of the field is `CORTEX_M55`"]
151    #[inline(always)]
152    pub fn is_cortex_m55(&self) -> bool {
153        *self == CPU0_TYPE_A::CORTEX_M55
154    }
155}
156#[doc = "Field `CPU0_HAS_SYSTCM` reader - CPU 0 has System TCM. Note that this is not the CPU's local ITCM or DTCM, but instead are TCMs implemented at system level."]
157pub type CPU0_HAS_SYSTCM_R = crate::BitReader<CPU0_HAS_SYSTCM_A>;
158#[doc = "CPU 0 has System TCM. Note that this is not the CPU's local ITCM or DTCM, but instead are TCMs implemented at system level.\n\nValue on reset: 0"]
159#[derive(Clone, Copy, Debug, PartialEq, Eq)]
160pub enum CPU0_HAS_SYSTCM_A {
161    #[doc = "0: Not included."]
162    NO = 0,
163    #[doc = "1: Included."]
164    YES = 1,
165}
166impl From<CPU0_HAS_SYSTCM_A> for bool {
167    #[inline(always)]
168    fn from(variant: CPU0_HAS_SYSTCM_A) -> Self {
169        variant as u8 != 0
170    }
171}
172impl CPU0_HAS_SYSTCM_R {
173    #[doc = "Get enumerated values variant"]
174    #[inline(always)]
175    pub fn variant(&self) -> CPU0_HAS_SYSTCM_A {
176        match self.bits {
177            false => CPU0_HAS_SYSTCM_A::NO,
178            true => CPU0_HAS_SYSTCM_A::YES,
179        }
180    }
181    #[doc = "Checks if the value of the field is `NO`"]
182    #[inline(always)]
183    pub fn is_no(&self) -> bool {
184        *self == CPU0_HAS_SYSTCM_A::NO
185    }
186    #[doc = "Checks if the value of the field is `YES`"]
187    #[inline(always)]
188    pub fn is_yes(&self) -> bool {
189        *self == CPU0_HAS_SYSTCM_A::YES
190    }
191}
192#[doc = "Field `CPU0_TCM_BANK_NUM` reader - The VM Bank that is the TCM memory for CPU 0."]
193pub type CPU0_TCM_BANK_NUM_R = crate::FieldReader<u8, u8>;
194#[doc = "Field `CPU1_TYPE` reader - CPU 1 Core Type"]
195pub type CPU1_TYPE_R = crate::FieldReader<u8, CPU1_TYPE_A>;
196#[doc = "CPU 1 Core Type\n\nValue on reset: 0"]
197#[derive(Clone, Copy, Debug, PartialEq, Eq)]
198#[repr(u8)]
199pub enum CPU1_TYPE_A {
200    #[doc = "0: Does not exist."]
201    NO = 0,
202}
203impl From<CPU1_TYPE_A> for u8 {
204    #[inline(always)]
205    fn from(variant: CPU1_TYPE_A) -> Self {
206        variant as _
207    }
208}
209impl CPU1_TYPE_R {
210    #[doc = "Get enumerated values variant"]
211    #[inline(always)]
212    pub fn variant(&self) -> Option<CPU1_TYPE_A> {
213        match self.bits {
214            0 => Some(CPU1_TYPE_A::NO),
215            _ => None,
216        }
217    }
218    #[doc = "Checks if the value of the field is `NO`"]
219    #[inline(always)]
220    pub fn is_no(&self) -> bool {
221        *self == CPU1_TYPE_A::NO
222    }
223}
224#[doc = "Field `CPU1_HAS_SYSTCM` reader - CPU 1 has System TCM. Note that this is not the CPU's local ITCM or DTCM, but instead are TCMs implemented at system level."]
225pub type CPU1_HAS_SYSTCM_R = crate::BitReader<CPU1_HAS_SYSTCM_A>;
226#[doc = "CPU 1 has System TCM. Note that this is not the CPU's local ITCM or DTCM, but instead are TCMs implemented at system level.\n\nValue on reset: 0"]
227#[derive(Clone, Copy, Debug, PartialEq, Eq)]
228pub enum CPU1_HAS_SYSTCM_A {
229    #[doc = "0: Not included."]
230    NO = 0,
231    #[doc = "1: Included."]
232    YES = 1,
233}
234impl From<CPU1_HAS_SYSTCM_A> for bool {
235    #[inline(always)]
236    fn from(variant: CPU1_HAS_SYSTCM_A) -> Self {
237        variant as u8 != 0
238    }
239}
240impl CPU1_HAS_SYSTCM_R {
241    #[doc = "Get enumerated values variant"]
242    #[inline(always)]
243    pub fn variant(&self) -> CPU1_HAS_SYSTCM_A {
244        match self.bits {
245            false => CPU1_HAS_SYSTCM_A::NO,
246            true => CPU1_HAS_SYSTCM_A::YES,
247        }
248    }
249    #[doc = "Checks if the value of the field is `NO`"]
250    #[inline(always)]
251    pub fn is_no(&self) -> bool {
252        *self == CPU1_HAS_SYSTCM_A::NO
253    }
254    #[doc = "Checks if the value of the field is `YES`"]
255    #[inline(always)]
256    pub fn is_yes(&self) -> bool {
257        *self == CPU1_HAS_SYSTCM_A::YES
258    }
259}
260#[doc = "Field `CPU1_TCM_BANK_NUM` reader - The VM Bank that is the TCM memory for CPU 1."]
261pub type CPU1_TCM_BANK_NUM_R = crate::FieldReader<u8, u8>;
262impl R {
263    #[doc = "Bits 0:3 - Number of Volatile Memory Banks."]
264    #[inline(always)]
265    pub fn num_vm_bank(&self) -> NUM_VM_BANK_R {
266        NUM_VM_BANK_R::new((self.bits & 0x0f) as u8)
267    }
268    #[doc = "Bits 4:8 - Volatile Memory Bank Address Width, where the size of each bank is equal to 2VM_ADDR_WIDTH bytes."]
269    #[inline(always)]
270    pub fn vm_addr_width(&self) -> VM_ADDR_WIDTH_R {
271        VM_ADDR_WIDTH_R::new(((self.bits >> 4) & 0x1f) as u8)
272    }
273    #[doc = "Bit 9 - CryptoCell Included."]
274    #[inline(always)]
275    pub fn has_crypto(&self) -> HAS_CRYPTO_R {
276        HAS_CRYPTO_R::new(((self.bits >> 9) & 1) != 0)
277    }
278    #[doc = "Bit 10 - Include CoreSight SoC-600 based Debug infrastructure."]
279    #[inline(always)]
280    pub fn has_css(&self) -> HAS_CSS_R {
281        HAS_CSS_R::new(((self.bits >> 10) & 1) != 0)
282    }
283    #[doc = "Bits 11:12 - Power Infrastructure Level"]
284    #[inline(always)]
285    pub fn pi_level(&self) -> PI_LEVEL_R {
286        PI_LEVEL_R::new(((self.bits >> 11) & 3) as u8)
287    }
288    #[doc = "Bits 16:18 - CPU 0 Core Type"]
289    #[inline(always)]
290    pub fn cpu0_type(&self) -> CPU0_TYPE_R {
291        CPU0_TYPE_R::new(((self.bits >> 16) & 7) as u8)
292    }
293    #[doc = "Bit 19 - CPU 0 has System TCM. Note that this is not the CPU's local ITCM or DTCM, but instead are TCMs implemented at system level."]
294    #[inline(always)]
295    pub fn cpu0_has_systcm(&self) -> CPU0_HAS_SYSTCM_R {
296        CPU0_HAS_SYSTCM_R::new(((self.bits >> 19) & 1) != 0)
297    }
298    #[doc = "Bits 20:23 - The VM Bank that is the TCM memory for CPU 0."]
299    #[inline(always)]
300    pub fn cpu0_tcm_bank_num(&self) -> CPU0_TCM_BANK_NUM_R {
301        CPU0_TCM_BANK_NUM_R::new(((self.bits >> 20) & 0x0f) as u8)
302    }
303    #[doc = "Bits 24:26 - CPU 1 Core Type"]
304    #[inline(always)]
305    pub fn cpu1_type(&self) -> CPU1_TYPE_R {
306        CPU1_TYPE_R::new(((self.bits >> 24) & 7) as u8)
307    }
308    #[doc = "Bit 27 - CPU 1 has System TCM. Note that this is not the CPU's local ITCM or DTCM, but instead are TCMs implemented at system level."]
309    #[inline(always)]
310    pub fn cpu1_has_systcm(&self) -> CPU1_HAS_SYSTCM_R {
311        CPU1_HAS_SYSTCM_R::new(((self.bits >> 27) & 1) != 0)
312    }
313    #[doc = "Bits 28:31 - The VM Bank that is the TCM memory for CPU 1."]
314    #[inline(always)]
315    pub fn cpu1_tcm_bank_num(&self) -> CPU1_TCM_BANK_NUM_R {
316        CPU1_TCM_BANK_NUM_R::new(((self.bits >> 28) & 0x0f) as u8)
317    }
318}
319#[doc = "System Hardware Configuration 0 register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sys_config0](index.html) module"]
320pub struct SYS_CONFIG0_SPEC;
321impl crate::RegisterSpec for SYS_CONFIG0_SPEC {
322    type Ux = u32;
323}
324#[doc = "`read()` method returns [sys_config0::R](R) reader structure"]
325impl crate::Readable for SYS_CONFIG0_SPEC {
326    type Reader = R;
327}
328#[doc = "`reset()` method sets SYS_CONFIG0 to value 0"]
329impl crate::Resettable for SYS_CONFIG0_SPEC {
330    #[inline(always)]
331    fn reset_value() -> Self::Ux {
332        0
333    }
334}
corstone300_pac/sysinfo/sys_config0.rs

corstone300_pac/sysinfo/
sys_config0.rs
