corstone300_pac/syscontrol/
reset_mask.rs

1// Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
2//
3// SPDX-License-Identifier: MIT
4
5#[doc = "Register `RESET_MASK` reader"]
6pub struct R(crate::R<RESET_MASK_SPEC>);
7impl core::ops::Deref for R {
8    type Target = crate::R<RESET_MASK_SPEC>;
9    #[inline(always)]
10    fn deref(&self) -> &Self::Target {
11        &self.0
12    }
13}
14impl From<crate::R<RESET_MASK_SPEC>> for R {
15    #[inline(always)]
16    fn from(reader: crate::R<RESET_MASK_SPEC>) -> Self {
17        R(reader)
18    }
19}
20#[doc = "Register `RESET_MASK` writer"]
21pub struct W(crate::W<RESET_MASK_SPEC>);
22impl core::ops::Deref for W {
23    type Target = crate::W<RESET_MASK_SPEC>;
24    #[inline(always)]
25    fn deref(&self) -> &Self::Target {
26        &self.0
27    }
28}
29impl core::ops::DerefMut for W {
30    #[inline(always)]
31    fn deref_mut(&mut self) -> &mut Self::Target {
32        &mut self.0
33    }
34}
35impl From<crate::W<RESET_MASK_SPEC>> for W {
36    #[inline(always)]
37    fn from(writer: crate::W<RESET_MASK_SPEC>) -> Self {
38        W(writer)
39    }
40}
41#[doc = "Field `NSWDRSTREQEN` reader - Enable NON-SECURE WATCHDOG Reset"]
42pub type NSWDRSTREQEN_R = crate::BitReader<NSWDRSTREQEN_A>;
43#[doc = "Enable NON-SECURE WATCHDOG Reset\n\nValue on reset: 0"]
44#[derive(Clone, Copy, Debug, PartialEq, Eq)]
45pub enum NSWDRSTREQEN_A {
46    #[doc = "1: Enable NON-SECURE WATCHDOG Reset"]
47    ENABLED = 1,
48    #[doc = "0: Disabled NON-SECURE WATCHDOG Reset"]
49    DISABLED = 0,
50}
51impl From<NSWDRSTREQEN_A> for bool {
52    #[inline(always)]
53    fn from(variant: NSWDRSTREQEN_A) -> Self {
54        variant as u8 != 0
55    }
56}
57impl NSWDRSTREQEN_R {
58    #[doc = "Get enumerated values variant"]
59    #[inline(always)]
60    pub fn variant(&self) -> NSWDRSTREQEN_A {
61        match self.bits {
62            true => NSWDRSTREQEN_A::ENABLED,
63            false => NSWDRSTREQEN_A::DISABLED,
64        }
65    }
66    #[doc = "Checks if the value of the field is `ENABLED`"]
67    #[inline(always)]
68    pub fn is_enabled(&self) -> bool {
69        *self == NSWDRSTREQEN_A::ENABLED
70    }
71    #[doc = "Checks if the value of the field is `DISABLED`"]
72    #[inline(always)]
73    pub fn is_disabled(&self) -> bool {
74        *self == NSWDRSTREQEN_A::DISABLED
75    }
76}
77#[doc = "Field `NSWDRSTREQEN` writer - Enable NON-SECURE WATCHDOG Reset"]
78pub type NSWDRSTREQEN_W<'a, const O: u8> =
79    crate::BitWriter<'a, u32, RESET_MASK_SPEC, NSWDRSTREQEN_A, O>;
80impl<'a, const O: u8> NSWDRSTREQEN_W<'a, O> {
81    #[doc = "Enable NON-SECURE WATCHDOG Reset"]
82    #[inline(always)]
83    pub fn enabled(self) -> &'a mut W {
84        self.variant(NSWDRSTREQEN_A::ENABLED)
85    }
86    #[doc = "Disabled NON-SECURE WATCHDOG Reset"]
87    #[inline(always)]
88    pub fn disabled(self) -> &'a mut W {
89        self.variant(NSWDRSTREQEN_A::DISABLED)
90    }
91}
92#[doc = "Field `CPU0RSTREQENRST` reader - CPU 0 Warm Reset Request Enable."]
93pub type CPU0RSTREQENRST_R = crate::BitReader<CPU0RSTREQENRST_A>;
94#[doc = "CPU 0 Warm Reset Request Enable.\n\nValue on reset: 0"]
95#[derive(Clone, Copy, Debug, PartialEq, Eq)]
96pub enum CPU0RSTREQENRST_A {
97    #[doc = "1: Enable Merging CPU 0 System Reset Request"]
98    ENABLED = 1,
99    #[doc = "0: Disabled Merging CPU 0 System Reset Request"]
100    DISABLED = 0,
101}
102impl From<CPU0RSTREQENRST_A> for bool {
103    #[inline(always)]
104    fn from(variant: CPU0RSTREQENRST_A) -> Self {
105        variant as u8 != 0
106    }
107}
108impl CPU0RSTREQENRST_R {
109    #[doc = "Get enumerated values variant"]
110    #[inline(always)]
111    pub fn variant(&self) -> CPU0RSTREQENRST_A {
112        match self.bits {
113            true => CPU0RSTREQENRST_A::ENABLED,
114            false => CPU0RSTREQENRST_A::DISABLED,
115        }
116    }
117    #[doc = "Checks if the value of the field is `ENABLED`"]
118    #[inline(always)]
119    pub fn is_enabled(&self) -> bool {
120        *self == CPU0RSTREQENRST_A::ENABLED
121    }
122    #[doc = "Checks if the value of the field is `DISABLED`"]
123    #[inline(always)]
124    pub fn is_disabled(&self) -> bool {
125        *self == CPU0RSTREQENRST_A::DISABLED
126    }
127}
128#[doc = "Field `CPU0RSTREQENRST` writer - CPU 0 Warm Reset Request Enable."]
129pub type CPU0RSTREQENRST_W<'a, const O: u8> =
130    crate::BitWriter<'a, u32, RESET_MASK_SPEC, CPU0RSTREQENRST_A, O>;
131impl<'a, const O: u8> CPU0RSTREQENRST_W<'a, O> {
132    #[doc = "Enable Merging CPU 0 System Reset Request"]
133    #[inline(always)]
134    pub fn enabled(self) -> &'a mut W {
135        self.variant(CPU0RSTREQENRST_A::ENABLED)
136    }
137    #[doc = "Disabled Merging CPU 0 System Reset Request"]
138    #[inline(always)]
139    pub fn disabled(self) -> &'a mut W {
140        self.variant(CPU0RSTREQENRST_A::DISABLED)
141    }
142}
143impl R {
144    #[doc = "Bit 1 - Enable NON-SECURE WATCHDOG Reset"]
145    #[inline(always)]
146    pub fn nswdrstreqen(&self) -> NSWDRSTREQEN_R {
147        NSWDRSTREQEN_R::new(((self.bits >> 1) & 1) != 0)
148    }
149    #[doc = "Bit 8 - CPU 0 Warm Reset Request Enable."]
150    #[inline(always)]
151    pub fn cpu0rstreqenrst(&self) -> CPU0RSTREQENRST_R {
152        CPU0RSTREQENRST_R::new(((self.bits >> 8) & 1) != 0)
153    }
154}
155impl W {
156    #[doc = "Bit 1 - Enable NON-SECURE WATCHDOG Reset"]
157    #[inline(always)]
158    pub fn nswdrstreqen(&mut self) -> NSWDRSTREQEN_W<1> {
159        NSWDRSTREQEN_W::new(self)
160    }
161    #[doc = "Bit 8 - CPU 0 Warm Reset Request Enable."]
162    #[inline(always)]
163    pub fn cpu0rstreqenrst(&mut self) -> CPU0RSTREQENRST_W<8> {
164        CPU0RSTREQENRST_W::new(self)
165    }
166    #[doc = "Writes raw bits to the register."]
167    #[inline(always)]
168    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
169        self.0.bits(bits);
170        self
171    }
172}
173#[doc = "Reset Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [reset_mask](index.html) module"]
174pub struct RESET_MASK_SPEC;
175impl crate::RegisterSpec for RESET_MASK_SPEC {
176    type Ux = u32;
177}
178#[doc = "`read()` method returns [reset_mask::R](R) reader structure"]
179impl crate::Readable for RESET_MASK_SPEC {
180    type Reader = R;
181}
182#[doc = "`write(|w| ..)` method takes [reset_mask::W](W) writer structure"]
183impl crate::Writable for RESET_MASK_SPEC {
184    type Writer = W;
185}
186#[doc = "`reset()` method sets RESET_MASK to value 0"]
187impl crate::Resettable for RESET_MASK_SPEC {
188    #[inline(always)]
189    fn reset_value() -> Self::Ux {
190        0
191    }
192}
corstone300_pac/syscontrol/reset_mask.rs

corstone300_pac/syscontrol/
reset_mask.rs
