corstone300_pac/syscontrol/
pwrctrl.rs

1// Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
2//
3// SPDX-License-Identifier: MIT
4
5#[doc = "Register `PWRCTRL` reader"]
6pub struct R(crate::R<PWRCTRL_SPEC>);
7impl core::ops::Deref for R {
8    type Target = crate::R<PWRCTRL_SPEC>;
9    #[inline(always)]
10    fn deref(&self) -> &Self::Target {
11        &self.0
12    }
13}
14impl From<crate::R<PWRCTRL_SPEC>> for R {
15    #[inline(always)]
16    fn from(reader: crate::R<PWRCTRL_SPEC>) -> Self {
17        R(reader)
18    }
19}
20#[doc = "Register `PWRCTRL` writer"]
21pub struct W(crate::W<PWRCTRL_SPEC>);
22impl core::ops::Deref for W {
23    type Target = crate::W<PWRCTRL_SPEC>;
24    #[inline(always)]
25    fn deref(&self) -> &Self::Target {
26        &self.0
27    }
28}
29impl core::ops::DerefMut for W {
30    #[inline(always)]
31    fn deref_mut(&mut self) -> &mut Self::Target {
32        &mut self.0
33    }
34}
35impl From<crate::W<PWRCTRL_SPEC>> for W {
36    #[inline(always)]
37    fn from(writer: crate::W<PWRCTRL_SPEC>) -> Self {
38        W(writer)
39    }
40}
41#[doc = "Field `PPU_ACCESS_UNLOCK` writer - PPU_ACCESS_FILTER write unlock. When 1, Both PPU_ACCESS_FILTER and this register bits can be written. When set to '0' the PPU_ACCESS_FILTER and this register bit will no longer writable, and PPU_ACCESS_UNLOCK will stay '0'."]
42pub type PPU_ACCESS_UNLOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, PWRCTRL_SPEC, bool, O>;
43#[doc = "Field `PPU_ACCESS_FILTER` reader - Filter Access to PPU Registers. When set to '1' only key PPU interrupt handling registers are open to write access, and all other PPU registers are read only. When set to '0' releases all PPU register to full access."]
44pub type PPU_ACCESS_FILTER_R = crate::BitReader<bool>;
45#[doc = "Field `PPU_ACCESS_FILTER` writer - Filter Access to PPU Registers. When set to '1' only key PPU interrupt handling registers are open to write access, and all other PPU registers are read only. When set to '0' releases all PPU register to full access."]
46pub type PPU_ACCESS_FILTER_W<'a, const O: u8> = crate::BitWriter<'a, u32, PWRCTRL_SPEC, bool, O>;
47impl R {
48    #[doc = "Bit 1 - Filter Access to PPU Registers. When set to '1' only key PPU interrupt handling registers are open to write access, and all other PPU registers are read only. When set to '0' releases all PPU register to full access."]
49    #[inline(always)]
50    pub fn ppu_access_filter(&self) -> PPU_ACCESS_FILTER_R {
51        PPU_ACCESS_FILTER_R::new(((self.bits >> 1) & 1) != 0)
52    }
53}
54impl W {
55    #[doc = "Bit 0 - PPU_ACCESS_FILTER write unlock. When 1, Both PPU_ACCESS_FILTER and this register bits can be written. When set to '0' the PPU_ACCESS_FILTER and this register bit will no longer writable, and PPU_ACCESS_UNLOCK will stay '0'."]
56    #[inline(always)]
57    pub fn ppu_access_unlock(&mut self) -> PPU_ACCESS_UNLOCK_W<0> {
58        PPU_ACCESS_UNLOCK_W::new(self)
59    }
60    #[doc = "Bit 1 - Filter Access to PPU Registers. When set to '1' only key PPU interrupt handling registers are open to write access, and all other PPU registers are read only. When set to '0' releases all PPU register to full access."]
61    #[inline(always)]
62    pub fn ppu_access_filter(&mut self) -> PPU_ACCESS_FILTER_W<1> {
63        PPU_ACCESS_FILTER_W::new(self)
64    }
65    #[doc = "Writes raw bits to the register."]
66    #[inline(always)]
67    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
68        self.0.bits(bits);
69        self
70    }
71}
72#[doc = "Power Configuration and Control.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pwrctrl](index.html) module"]
73pub struct PWRCTRL_SPEC;
74impl crate::RegisterSpec for PWRCTRL_SPEC {
75    type Ux = u32;
76}
77#[doc = "`read()` method returns [pwrctrl::R](R) reader structure"]
78impl crate::Readable for PWRCTRL_SPEC {
79    type Reader = R;
80}
81#[doc = "`write(|w| ..)` method takes [pwrctrl::W](W) writer structure"]
82impl crate::Writable for PWRCTRL_SPEC {
83    type Writer = W;
84}
85#[doc = "`reset()` method sets PWRCTRL to value 0x03"]
86impl crate::Resettable for PWRCTRL_SPEC {
87    #[inline(always)]
88    fn reset_value() -> Self::Ux {
89        0x03
90    }
91}
corstone300_pac/syscontrol/pwrctrl.rs

corstone300_pac/syscontrol/
pwrctrl.rs
