corstone300_pac/syscontrol/
cpuwait.rs

1// Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
2//
3// SPDX-License-Identifier: MIT
4
5#[doc = "Register `CPUWAIT` reader"]
6pub struct R(crate::R<CPUWAIT_SPEC>);
7impl core::ops::Deref for R {
8    type Target = crate::R<CPUWAIT_SPEC>;
9    #[inline(always)]
10    fn deref(&self) -> &Self::Target {
11        &self.0
12    }
13}
14impl From<crate::R<CPUWAIT_SPEC>> for R {
15    #[inline(always)]
16    fn from(reader: crate::R<CPUWAIT_SPEC>) -> Self {
17        R(reader)
18    }
19}
20#[doc = "Register `CPUWAIT` writer"]
21pub struct W(crate::W<CPUWAIT_SPEC>);
22impl core::ops::Deref for W {
23    type Target = crate::W<CPUWAIT_SPEC>;
24    #[inline(always)]
25    fn deref(&self) -> &Self::Target {
26        &self.0
27    }
28}
29impl core::ops::DerefMut for W {
30    #[inline(always)]
31    fn deref_mut(&mut self) -> &mut Self::Target {
32        &mut self.0
33    }
34}
35impl From<crate::W<CPUWAIT_SPEC>> for W {
36    #[inline(always)]
37    fn from(writer: crate::W<CPUWAIT_SPEC>) -> Self {
38        W(writer)
39    }
40}
41#[doc = "Field `CPU0WAIT` reader - CPU 0 waits at boot and whether CPU1 powers up"]
42pub type CPU0WAIT_R = crate::BitReader<CPU0WAIT_A>;
43#[doc = "CPU 0 waits at boot and whether CPU1 powers up\n\nValue on reset: 0"]
44#[derive(Clone, Copy, Debug, PartialEq, Eq)]
45pub enum CPU0WAIT_A {
46    #[doc = "0: CPU0 boot normally. From Power ON reset, nSRST reset or Watchdog Reset, CPU 1 powers up"]
47    NORMALLY_OR_POWERUP = 0,
48    #[doc = "1: CPU0 wait. From Power ON reset, nSRST reset or Watchdog Reset, CPU 1 do not power up"]
49    WAIT_OR_NO_POWERUP = 1,
50}
51impl From<CPU0WAIT_A> for bool {
52    #[inline(always)]
53    fn from(variant: CPU0WAIT_A) -> Self {
54        variant as u8 != 0
55    }
56}
57impl CPU0WAIT_R {
58    #[doc = "Get enumerated values variant"]
59    #[inline(always)]
60    pub fn variant(&self) -> CPU0WAIT_A {
61        match self.bits {
62            false => CPU0WAIT_A::NORMALLY_OR_POWERUP,
63            true => CPU0WAIT_A::WAIT_OR_NO_POWERUP,
64        }
65    }
66    #[doc = "Checks if the value of the field is `NORMALLY_OR_POWERUP`"]
67    #[inline(always)]
68    pub fn is_normally_or_powerup(&self) -> bool {
69        *self == CPU0WAIT_A::NORMALLY_OR_POWERUP
70    }
71    #[doc = "Checks if the value of the field is `WAIT_OR_NO_POWERUP`"]
72    #[inline(always)]
73    pub fn is_wait_or_no_powerup(&self) -> bool {
74        *self == CPU0WAIT_A::WAIT_OR_NO_POWERUP
75    }
76}
77#[doc = "Field `CPU0WAIT` writer - CPU 0 waits at boot and whether CPU1 powers up"]
78pub type CPU0WAIT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CPUWAIT_SPEC, CPU0WAIT_A, O>;
79impl<'a, const O: u8> CPU0WAIT_W<'a, O> {
80    #[doc = "CPU0 boot normally. From Power ON reset, nSRST reset or Watchdog Reset, CPU 1 powers up"]
81    #[inline(always)]
82    pub fn normally_or_powerup(self) -> &'a mut W {
83        self.variant(CPU0WAIT_A::NORMALLY_OR_POWERUP)
84    }
85    #[doc = "CPU0 wait. From Power ON reset, nSRST reset or Watchdog Reset, CPU 1 do not power up"]
86    #[inline(always)]
87    pub fn wait_or_no_powerup(self) -> &'a mut W {
88        self.variant(CPU0WAIT_A::WAIT_OR_NO_POWERUP)
89    }
90}
91impl R {
92    #[doc = "Bit 0 - CPU 0 waits at boot and whether CPU1 powers up"]
93    #[inline(always)]
94    pub fn cpu0wait(&self) -> CPU0WAIT_R {
95        CPU0WAIT_R::new((self.bits & 1) != 0)
96    }
97}
98impl W {
99    #[doc = "Bit 0 - CPU 0 waits at boot and whether CPU1 powers up"]
100    #[inline(always)]
101    pub fn cpu0wait(&mut self) -> CPU0WAIT_W<0> {
102        CPU0WAIT_W::new(self)
103    }
104    #[doc = "Writes raw bits to the register."]
105    #[inline(always)]
106    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
107        self.0.bits(bits);
108        self
109    }
110}
111#[doc = "CPU Boot wait control after reset\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpuwait](index.html) module"]
112pub struct CPUWAIT_SPEC;
113impl crate::RegisterSpec for CPUWAIT_SPEC {
114    type Ux = u32;
115}
116#[doc = "`read()` method returns [cpuwait::R](R) reader structure"]
117impl crate::Readable for CPUWAIT_SPEC {
118    type Reader = R;
119}
120#[doc = "`write(|w| ..)` method takes [cpuwait::W](W) writer structure"]
121impl crate::Writable for CPUWAIT_SPEC {
122    type Writer = W;
123}
124#[doc = "`reset()` method sets CPUWAIT to value 0"]
125impl crate::Resettable for CPUWAIT_SPEC {
126    #[inline(always)]
127    fn reset_value() -> Self::Ux {
128        0
129    }
130}
corstone300_pac/syscontrol/cpuwait.rs

corstone300_pac/syscontrol/
cpuwait.rs
