corstone300_pac/syscontrol/
clk_cfg1.rs

1// Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
2//
3// SPDX-License-Identifier: MIT
4
5#[doc = "Register `CLK_CFG1` reader"]
6pub struct R(crate::R<CLK_CFG1_SPEC>);
7impl core::ops::Deref for R {
8    type Target = crate::R<CLK_CFG1_SPEC>;
9    #[inline(always)]
10    fn deref(&self) -> &Self::Target {
11        &self.0
12    }
13}
14impl From<crate::R<CLK_CFG1_SPEC>> for R {
15    #[inline(always)]
16    fn from(reader: crate::R<CLK_CFG1_SPEC>) -> Self {
17        R(reader)
18    }
19}
20#[doc = "Register `CLK_CFG1` writer"]
21pub struct W(crate::W<CLK_CFG1_SPEC>);
22impl core::ops::Deref for W {
23    type Target = crate::W<CLK_CFG1_SPEC>;
24    #[inline(always)]
25    fn deref(&self) -> &Self::Target {
26        &self.0
27    }
28}
29impl core::ops::DerefMut for W {
30    #[inline(always)]
31    fn deref_mut(&mut self) -> &mut Self::Target {
32        &mut self.0
33    }
34}
35impl From<crate::W<CLK_CFG1_SPEC>> for W {
36    #[inline(always)]
37    fn from(writer: crate::W<CLK_CFG1_SPEC>) -> Self {
38        W(writer)
39    }
40}
41#[doc = "Field `SYSCLKCFG` reader - Clock Configuration value that drives SYSCLKCFG signals."]
42pub type SYSCLKCFG_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `SYSCLKCFG` writer - Clock Configuration value that drives SYSCLKCFG signals."]
44pub type SYSCLKCFG_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_CFG1_SPEC, u8, u8, 4, O>;
45#[doc = "Field `AONCLKCFG` reader - Clock Configuration value that drives AONCLKCFG signals."]
46pub type AONCLKCFG_R = crate::FieldReader<u8, u8>;
47#[doc = "Field `AONCLKCFG` writer - Clock Configuration value that drives AONCLKCFG signals."]
48pub type AONCLKCFG_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_CFG1_SPEC, u8, u8, 4, O>;
49#[doc = "Field `SYSCLKCFGSTATUS` reader - Clock Configuration Status value that reports the status of clock control for SYSCLK."]
50pub type SYSCLKCFGSTATUS_R = crate::FieldReader<u8, u8>;
51#[doc = "Field `AONCLKCFGSTATUS` reader - Clock Configuration Status value that reports the status of clock control for AONCLK."]
52pub type AONCLKCFGSTATUS_R = crate::FieldReader<u8, u8>;
53#[doc = "Field `AONCLKCFGSTATUS` writer - Clock Configuration Status value that reports the status of clock control for AONCLK."]
54pub type AONCLKCFGSTATUS_W<'a, const O: u8> =
55    crate::FieldWriter<'a, u32, CLK_CFG1_SPEC, u8, u8, 4, O>;
56impl R {
57    #[doc = "Bits 0:3 - Clock Configuration value that drives SYSCLKCFG signals."]
58    #[inline(always)]
59    pub fn sysclkcfg(&self) -> SYSCLKCFG_R {
60        SYSCLKCFG_R::new((self.bits & 0x0f) as u8)
61    }
62    #[doc = "Bits 4:7 - Clock Configuration value that drives AONCLKCFG signals."]
63    #[inline(always)]
64    pub fn aonclkcfg(&self) -> AONCLKCFG_R {
65        AONCLKCFG_R::new(((self.bits >> 4) & 0x0f) as u8)
66    }
67    #[doc = "Bits 16:19 - Clock Configuration Status value that reports the status of clock control for SYSCLK."]
68    #[inline(always)]
69    pub fn sysclkcfgstatus(&self) -> SYSCLKCFGSTATUS_R {
70        SYSCLKCFGSTATUS_R::new(((self.bits >> 16) & 0x0f) as u8)
71    }
72    #[doc = "Bits 20:23 - Clock Configuration Status value that reports the status of clock control for AONCLK."]
73    #[inline(always)]
74    pub fn aonclkcfgstatus(&self) -> AONCLKCFGSTATUS_R {
75        AONCLKCFGSTATUS_R::new(((self.bits >> 20) & 0x0f) as u8)
76    }
77}
78impl W {
79    #[doc = "Bits 0:3 - Clock Configuration value that drives SYSCLKCFG signals."]
80    #[inline(always)]
81    pub fn sysclkcfg(&mut self) -> SYSCLKCFG_W<0> {
82        SYSCLKCFG_W::new(self)
83    }
84    #[doc = "Bits 4:7 - Clock Configuration value that drives AONCLKCFG signals."]
85    #[inline(always)]
86    pub fn aonclkcfg(&mut self) -> AONCLKCFG_W<4> {
87        AONCLKCFG_W::new(self)
88    }
89    #[doc = "Bits 20:23 - Clock Configuration Status value that reports the status of clock control for AONCLK."]
90    #[inline(always)]
91    pub fn aonclkcfgstatus(&mut self) -> AONCLKCFGSTATUS_W<20> {
92        AONCLKCFGSTATUS_W::new(self)
93    }
94    #[doc = "Writes raw bits to the register."]
95    #[inline(always)]
96    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
97        self.0.bits(bits);
98        self
99    }
100}
101#[doc = "Clock Configuration Register 1.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_cfg1](index.html) module"]
102pub struct CLK_CFG1_SPEC;
103impl crate::RegisterSpec for CLK_CFG1_SPEC {
104    type Ux = u32;
105}
106#[doc = "`read()` method returns [clk_cfg1::R](R) reader structure"]
107impl crate::Readable for CLK_CFG1_SPEC {
108    type Reader = R;
109}
110#[doc = "`write(|w| ..)` method takes [clk_cfg1::W](W) writer structure"]
111impl crate::Writable for CLK_CFG1_SPEC {
112    type Writer = W;
113}
114#[doc = "`reset()` method sets CLK_CFG1 to value 0"]
115impl crate::Resettable for CLK_CFG1_SPEC {
116    #[inline(always)]
117    fn reset_value() -> Self::Ux {
118        0
119    }
120}
corstone300_pac/syscontrol/clk_cfg1.rs

corstone300_pac/syscontrol/
clk_cfg1.rs
