corstone300_pac/syscontrol/
clk_cfg0.rs

1// Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
2//
3// SPDX-License-Identifier: MIT
4
5#[doc = "Register `CLK_CFG0` reader"]
6pub struct R(crate::R<CLK_CFG0_SPEC>);
7impl core::ops::Deref for R {
8    type Target = crate::R<CLK_CFG0_SPEC>;
9    #[inline(always)]
10    fn deref(&self) -> &Self::Target {
11        &self.0
12    }
13}
14impl From<crate::R<CLK_CFG0_SPEC>> for R {
15    #[inline(always)]
16    fn from(reader: crate::R<CLK_CFG0_SPEC>) -> Self {
17        R(reader)
18    }
19}
20#[doc = "Register `CLK_CFG0` writer"]
21pub struct W(crate::W<CLK_CFG0_SPEC>);
22impl core::ops::Deref for W {
23    type Target = crate::W<CLK_CFG0_SPEC>;
24    #[inline(always)]
25    fn deref(&self) -> &Self::Target {
26        &self.0
27    }
28}
29impl core::ops::DerefMut for W {
30    #[inline(always)]
31    fn deref_mut(&mut self) -> &mut Self::Target {
32        &mut self.0
33    }
34}
35impl From<crate::W<CLK_CFG0_SPEC>> for W {
36    #[inline(always)]
37    fn from(writer: crate::W<CLK_CFG0_SPEC>) -> Self {
38        W(writer)
39    }
40}
41#[doc = "Field `CPU0CLKCFG` reader - Clock Configuration value that drives CPU0CLKCFG signals."]
42pub type CPU0CLKCFG_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `CPU0CLKCFG` writer - Clock Configuration value that drives CPU0CLKCFG signals."]
44pub type CPU0CLKCFG_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLK_CFG0_SPEC, u8, u8, 4, O>;
45#[doc = "Field `CPU0CLKCFGSTATUS` reader - Clock Configuration Status value that reports the status of clock control for CPU0CLK."]
46pub type CPU0CLKCFGSTATUS_R = crate::FieldReader<u8, u8>;
47impl R {
48    #[doc = "Bits 0:3 - Clock Configuration value that drives CPU0CLKCFG signals."]
49    #[inline(always)]
50    pub fn cpu0clkcfg(&self) -> CPU0CLKCFG_R {
51        CPU0CLKCFG_R::new((self.bits & 0x0f) as u8)
52    }
53    #[doc = "Bits 16:19 - Clock Configuration Status value that reports the status of clock control for CPU0CLK."]
54    #[inline(always)]
55    pub fn cpu0clkcfgstatus(&self) -> CPU0CLKCFGSTATUS_R {
56        CPU0CLKCFGSTATUS_R::new(((self.bits >> 16) & 0x0f) as u8)
57    }
58}
59impl W {
60    #[doc = "Bits 0:3 - Clock Configuration value that drives CPU0CLKCFG signals."]
61    #[inline(always)]
62    pub fn cpu0clkcfg(&mut self) -> CPU0CLKCFG_W<0> {
63        CPU0CLKCFG_W::new(self)
64    }
65    #[doc = "Writes raw bits to the register."]
66    #[inline(always)]
67    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
68        self.0.bits(bits);
69        self
70    }
71}
72#[doc = "Clock Configuration Register 0.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clk_cfg0](index.html) module"]
73pub struct CLK_CFG0_SPEC;
74impl crate::RegisterSpec for CLK_CFG0_SPEC {
75    type Ux = u32;
76}
77#[doc = "`read()` method returns [clk_cfg0::R](R) reader structure"]
78impl crate::Readable for CLK_CFG0_SPEC {
79    type Reader = R;
80}
81#[doc = "`write(|w| ..)` method takes [clk_cfg0::W](W) writer structure"]
82impl crate::Writable for CLK_CFG0_SPEC {
83    type Writer = W;
84}
85#[doc = "`reset()` method sets CLK_CFG0 to value 0"]
86impl crate::Resettable for CLK_CFG0_SPEC {
87    #[inline(always)]
88    fn reset_value() -> Self::Ux {
89        0
90    }
91}
corstone300_pac/syscontrol/clk_cfg0.rs

corstone300_pac/syscontrol/
clk_cfg0.rs
