corstone300_pac/ssp0/
tdr.rs

1// Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
2//
3// SPDX-License-Identifier: MIT
4
5#[doc = "Register `TDR` reader"]
6pub struct R(crate::R<TDR_SPEC>);
7impl core::ops::Deref for R {
8    type Target = crate::R<TDR_SPEC>;
9    #[inline(always)]
10    fn deref(&self) -> &Self::Target {
11        &self.0
12    }
13}
14impl From<crate::R<TDR_SPEC>> for R {
15    #[inline(always)]
16    fn from(reader: crate::R<TDR_SPEC>) -> Self {
17        R(reader)
18    }
19}
20#[doc = "Register `TDR` writer"]
21pub struct W(crate::W<TDR_SPEC>);
22impl core::ops::Deref for W {
23    type Target = crate::W<TDR_SPEC>;
24    #[inline(always)]
25    fn deref(&self) -> &Self::Target {
26        &self.0
27    }
28}
29impl core::ops::DerefMut for W {
30    #[inline(always)]
31    fn deref_mut(&mut self) -> &mut Self::Target {
32        &mut self.0
33    }
34}
35impl From<crate::W<TDR_SPEC>> for W {
36    #[inline(always)]
37    fn from(writer: crate::W<TDR_SPEC>) -> Self {
38        W(writer)
39    }
40}
41#[doc = "Field `DATA` reader - When the TESTFIFO signal is asserted, data is written into the receive FIFO and read out of the transmit FIFO"]
42pub type DATA_R = crate::FieldReader<u16, u16>;
43#[doc = "Field `DATA` writer - When the TESTFIFO signal is asserted, data is written into the receive FIFO and read out of the transmit FIFO"]
44pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, TDR_SPEC, u16, u16, 16, O>;
45impl R {
46    #[doc = "Bits 0:15 - When the TESTFIFO signal is asserted, data is written into the receive FIFO and read out of the transmit FIFO"]
47    #[inline(always)]
48    pub fn data(&self) -> DATA_R {
49        DATA_R::new((self.bits & 0xffff) as u16)
50    }
51}
52impl W {
53    #[doc = "Bits 0:15 - When the TESTFIFO signal is asserted, data is written into the receive FIFO and read out of the transmit FIFO"]
54    #[inline(always)]
55    pub fn data(&mut self) -> DATA_W<0> {
56        DATA_W::new(self)
57    }
58    #[doc = "Writes raw bits to the register."]
59    #[inline(always)]
60    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
61        self.0.bits(bits);
62        self
63    }
64}
65#[doc = "Test data register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tdr](index.html) module"]
66pub struct TDR_SPEC;
67impl crate::RegisterSpec for TDR_SPEC {
68    type Ux = u32;
69}
70#[doc = "`read()` method returns [tdr::R](R) reader structure"]
71impl crate::Readable for TDR_SPEC {
72    type Reader = R;
73}
74#[doc = "`write(|w| ..)` method takes [tdr::W](W) writer structure"]
75impl crate::Writable for TDR_SPEC {
76    type Writer = W;
77}
78#[doc = "`reset()` method sets TDR to value 0"]
79impl crate::Resettable for TDR_SPEC {
80    #[inline(always)]
81    fn reset_value() -> Self::Ux {
82        0
83    }
84}
corstone300_pac/ssp0/tdr.rs

corstone300_pac/ssp0/
tdr.rs
