corstone300_pac/ssp0/
mis.rs

1// Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
2//
3// SPDX-License-Identifier: MIT
4
5#[doc = "Register `MIS` reader"]
6pub struct R(crate::R<MIS_SPEC>);
7impl core::ops::Deref for R {
8    type Target = crate::R<MIS_SPEC>;
9    #[inline(always)]
10    fn deref(&self) -> &Self::Target {
11        &self.0
12    }
13}
14impl From<crate::R<MIS_SPEC>> for R {
15    #[inline(always)]
16    fn from(reader: crate::R<MIS_SPEC>) -> Self {
17        R(reader)
18    }
19}
20#[doc = "Register `MIS` writer"]
21pub struct W(crate::W<MIS_SPEC>);
22impl core::ops::Deref for W {
23    type Target = crate::W<MIS_SPEC>;
24    #[inline(always)]
25    fn deref(&self) -> &Self::Target {
26        &self.0
27    }
28}
29impl core::ops::DerefMut for W {
30    #[inline(always)]
31    fn deref_mut(&mut self) -> &mut Self::Target {
32        &mut self.0
33    }
34}
35impl From<crate::W<MIS_SPEC>> for W {
36    #[inline(always)]
37    fn from(writer: crate::W<MIS_SPEC>) -> Self {
38        W(writer)
39    }
40}
41#[doc = "Field `RORMIS` reader - receive over run masked interrupt state"]
42pub type RORMIS_R = crate::BitReader<bool>;
43#[doc = "Field `RORMIS` writer - receive over run masked interrupt state"]
44pub type RORMIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, MIS_SPEC, bool, O>;
45#[doc = "Field `RTMIS` reader - receive timeout masked interrupt state"]
46pub type RTMIS_R = crate::BitReader<bool>;
47#[doc = "Field `RTMIS` writer - receive timeout masked interrupt state"]
48pub type RTMIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, MIS_SPEC, bool, O>;
49#[doc = "Field `RXMIS` reader - receive FIFO masked interrupt state"]
50pub type RXMIS_R = crate::BitReader<bool>;
51#[doc = "Field `RXMIS` writer - receive FIFO masked interrupt state"]
52pub type RXMIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, MIS_SPEC, bool, O>;
53#[doc = "Field `TXMIS` reader - transmit FIFO masked interrupt state"]
54pub type TXMIS_R = crate::BitReader<bool>;
55#[doc = "Field `TXMIS` writer - transmit FIFO masked interrupt state"]
56pub type TXMIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, MIS_SPEC, bool, O>;
57impl R {
58    #[doc = "Bit 0 - receive over run masked interrupt state"]
59    #[inline(always)]
60    pub fn rormis(&self) -> RORMIS_R {
61        RORMIS_R::new((self.bits & 1) != 0)
62    }
63    #[doc = "Bit 1 - receive timeout masked interrupt state"]
64    #[inline(always)]
65    pub fn rtmis(&self) -> RTMIS_R {
66        RTMIS_R::new(((self.bits >> 1) & 1) != 0)
67    }
68    #[doc = "Bit 2 - receive FIFO masked interrupt state"]
69    #[inline(always)]
70    pub fn rxmis(&self) -> RXMIS_R {
71        RXMIS_R::new(((self.bits >> 2) & 1) != 0)
72    }
73    #[doc = "Bit 3 - transmit FIFO masked interrupt state"]
74    #[inline(always)]
75    pub fn txmis(&self) -> TXMIS_R {
76        TXMIS_R::new(((self.bits >> 3) & 1) != 0)
77    }
78}
79impl W {
80    #[doc = "Bit 0 - receive over run masked interrupt state"]
81    #[inline(always)]
82    pub fn rormis(&mut self) -> RORMIS_W<0> {
83        RORMIS_W::new(self)
84    }
85    #[doc = "Bit 1 - receive timeout masked interrupt state"]
86    #[inline(always)]
87    pub fn rtmis(&mut self) -> RTMIS_W<1> {
88        RTMIS_W::new(self)
89    }
90    #[doc = "Bit 2 - receive FIFO masked interrupt state"]
91    #[inline(always)]
92    pub fn rxmis(&mut self) -> RXMIS_W<2> {
93        RXMIS_W::new(self)
94    }
95    #[doc = "Bit 3 - transmit FIFO masked interrupt state"]
96    #[inline(always)]
97    pub fn txmis(&mut self) -> TXMIS_W<3> {
98        TXMIS_W::new(self)
99    }
100    #[doc = "Writes raw bits to the register."]
101    #[inline(always)]
102    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
103        self.0.bits(bits);
104        self
105    }
106}
107#[doc = "Masked interrupt status register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mis](index.html) module"]
108pub struct MIS_SPEC;
109impl crate::RegisterSpec for MIS_SPEC {
110    type Ux = u32;
111}
112#[doc = "`read()` method returns [mis::R](R) reader structure"]
113impl crate::Readable for MIS_SPEC {
114    type Reader = R;
115}
116#[doc = "`write(|w| ..)` method takes [mis::W](W) writer structure"]
117impl crate::Writable for MIS_SPEC {
118    type Writer = W;
119}
120#[doc = "`reset()` method sets MIS to value 0"]
121impl crate::Resettable for MIS_SPEC {
122    #[inline(always)]
123    fn reset_value() -> Self::Ux {
124        0
125    }
126}
corstone300_pac/ssp0/mis.rs

corstone300_pac/ssp0/
mis.rs
