corstone300_pac/ssp0/
imsc.rs

1// Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
2//
3// SPDX-License-Identifier: MIT
4
5#[doc = "Register `IMSC` reader"]
6pub struct R(crate::R<IMSC_SPEC>);
7impl core::ops::Deref for R {
8    type Target = crate::R<IMSC_SPEC>;
9    #[inline(always)]
10    fn deref(&self) -> &Self::Target {
11        &self.0
12    }
13}
14impl From<crate::R<IMSC_SPEC>> for R {
15    #[inline(always)]
16    fn from(reader: crate::R<IMSC_SPEC>) -> Self {
17        R(reader)
18    }
19}
20#[doc = "Register `IMSC` writer"]
21pub struct W(crate::W<IMSC_SPEC>);
22impl core::ops::Deref for W {
23    type Target = crate::W<IMSC_SPEC>;
24    #[inline(always)]
25    fn deref(&self) -> &Self::Target {
26        &self.0
27    }
28}
29impl core::ops::DerefMut for W {
30    #[inline(always)]
31    fn deref_mut(&mut self) -> &mut Self::Target {
32        &mut self.0
33    }
34}
35impl From<crate::W<IMSC_SPEC>> for W {
36    #[inline(always)]
37    fn from(writer: crate::W<IMSC_SPEC>) -> Self {
38        W(writer)
39    }
40}
41#[doc = "Field `RORIM` reader - Receive overrun interrupt mask"]
42pub type RORIM_R = crate::BitReader<RORIM_A>;
43#[doc = "Receive overrun interrupt mask\n\nValue on reset: 0"]
44#[derive(Clone, Copy, Debug, PartialEq, Eq)]
45pub enum RORIM_A {
46    #[doc = "0: Receive FIFO written to while full condition interrupt is masked"]
47    MASKED = 0,
48    #[doc = "1: Receive FIFO written to while full condition interrupt is not masked"]
49    NOT_MASKED = 1,
50}
51impl From<RORIM_A> for bool {
52    #[inline(always)]
53    fn from(variant: RORIM_A) -> Self {
54        variant as u8 != 0
55    }
56}
57impl RORIM_R {
58    #[doc = "Get enumerated values variant"]
59    #[inline(always)]
60    pub fn variant(&self) -> RORIM_A {
61        match self.bits {
62            false => RORIM_A::MASKED,
63            true => RORIM_A::NOT_MASKED,
64        }
65    }
66    #[doc = "Checks if the value of the field is `MASKED`"]
67    #[inline(always)]
68    pub fn is_masked(&self) -> bool {
69        *self == RORIM_A::MASKED
70    }
71    #[doc = "Checks if the value of the field is `NOT_MASKED`"]
72    #[inline(always)]
73    pub fn is_not_masked(&self) -> bool {
74        *self == RORIM_A::NOT_MASKED
75    }
76}
77#[doc = "Field `RORIM` writer - Receive overrun interrupt mask"]
78pub type RORIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, RORIM_A, O>;
79impl<'a, const O: u8> RORIM_W<'a, O> {
80    #[doc = "Receive FIFO written to while full condition interrupt is masked"]
81    #[inline(always)]
82    pub fn masked(self) -> &'a mut W {
83        self.variant(RORIM_A::MASKED)
84    }
85    #[doc = "Receive FIFO written to while full condition interrupt is not masked"]
86    #[inline(always)]
87    pub fn not_masked(self) -> &'a mut W {
88        self.variant(RORIM_A::NOT_MASKED)
89    }
90}
91#[doc = "Field `RTIM` reader - Receive timeout interrupt mask"]
92pub type RTIM_R = crate::BitReader<RTIM_A>;
93#[doc = "Receive timeout interrupt mask\n\nValue on reset: 0"]
94#[derive(Clone, Copy, Debug, PartialEq, Eq)]
95pub enum RTIM_A {
96    #[doc = "0: Receive FIFO not empty or no read prior to timeout period interrupt is masked"]
97    MASKED = 0,
98    #[doc = "1: Receive FIFO not empty or no read prior to timeout period interrupt is not masked"]
99    NOT_MASKED = 1,
100}
101impl From<RTIM_A> for bool {
102    #[inline(always)]
103    fn from(variant: RTIM_A) -> Self {
104        variant as u8 != 0
105    }
106}
107impl RTIM_R {
108    #[doc = "Get enumerated values variant"]
109    #[inline(always)]
110    pub fn variant(&self) -> RTIM_A {
111        match self.bits {
112            false => RTIM_A::MASKED,
113            true => RTIM_A::NOT_MASKED,
114        }
115    }
116    #[doc = "Checks if the value of the field is `MASKED`"]
117    #[inline(always)]
118    pub fn is_masked(&self) -> bool {
119        *self == RTIM_A::MASKED
120    }
121    #[doc = "Checks if the value of the field is `NOT_MASKED`"]
122    #[inline(always)]
123    pub fn is_not_masked(&self) -> bool {
124        *self == RTIM_A::NOT_MASKED
125    }
126}
127#[doc = "Field `RTIM` writer - Receive timeout interrupt mask"]
128pub type RTIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, RTIM_A, O>;
129impl<'a, const O: u8> RTIM_W<'a, O> {
130    #[doc = "Receive FIFO not empty or no read prior to timeout period interrupt is masked"]
131    #[inline(always)]
132    pub fn masked(self) -> &'a mut W {
133        self.variant(RTIM_A::MASKED)
134    }
135    #[doc = "Receive FIFO not empty or no read prior to timeout period interrupt is not masked"]
136    #[inline(always)]
137    pub fn not_masked(self) -> &'a mut W {
138        self.variant(RTIM_A::NOT_MASKED)
139    }
140}
141#[doc = "Field `RXIM` reader - Receive FIFO interrupt mask"]
142pub type RXIM_R = crate::BitReader<RXIM_A>;
143#[doc = "Receive FIFO interrupt mask\n\nValue on reset: 0"]
144#[derive(Clone, Copy, Debug, PartialEq, Eq)]
145pub enum RXIM_A {
146    #[doc = "0: Receive FIFO half full or less condition interrupt is masked"]
147    MASKED = 0,
148    #[doc = "1: Receive FIFO half full or less condition interrupt is not masked"]
149    NOT_MASKED = 1,
150}
151impl From<RXIM_A> for bool {
152    #[inline(always)]
153    fn from(variant: RXIM_A) -> Self {
154        variant as u8 != 0
155    }
156}
157impl RXIM_R {
158    #[doc = "Get enumerated values variant"]
159    #[inline(always)]
160    pub fn variant(&self) -> RXIM_A {
161        match self.bits {
162            false => RXIM_A::MASKED,
163            true => RXIM_A::NOT_MASKED,
164        }
165    }
166    #[doc = "Checks if the value of the field is `MASKED`"]
167    #[inline(always)]
168    pub fn is_masked(&self) -> bool {
169        *self == RXIM_A::MASKED
170    }
171    #[doc = "Checks if the value of the field is `NOT_MASKED`"]
172    #[inline(always)]
173    pub fn is_not_masked(&self) -> bool {
174        *self == RXIM_A::NOT_MASKED
175    }
176}
177#[doc = "Field `RXIM` writer - Receive FIFO interrupt mask"]
178pub type RXIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, RXIM_A, O>;
179impl<'a, const O: u8> RXIM_W<'a, O> {
180    #[doc = "Receive FIFO half full or less condition interrupt is masked"]
181    #[inline(always)]
182    pub fn masked(self) -> &'a mut W {
183        self.variant(RXIM_A::MASKED)
184    }
185    #[doc = "Receive FIFO half full or less condition interrupt is not masked"]
186    #[inline(always)]
187    pub fn not_masked(self) -> &'a mut W {
188        self.variant(RXIM_A::NOT_MASKED)
189    }
190}
191#[doc = "Field `TXIM` reader - Transmit FIFO interrupt mask"]
192pub type TXIM_R = crate::BitReader<TXIM_A>;
193#[doc = "Transmit FIFO interrupt mask\n\nValue on reset: 0"]
194#[derive(Clone, Copy, Debug, PartialEq, Eq)]
195pub enum TXIM_A {
196    #[doc = "0: Transmit FIFO half empty or less condition interrupt is masked"]
197    MASKED = 0,
198    #[doc = "1: Transmit FIFO half empty or less condition interrupt is not masked"]
199    NOT_MASKED = 1,
200}
201impl From<TXIM_A> for bool {
202    #[inline(always)]
203    fn from(variant: TXIM_A) -> Self {
204        variant as u8 != 0
205    }
206}
207impl TXIM_R {
208    #[doc = "Get enumerated values variant"]
209    #[inline(always)]
210    pub fn variant(&self) -> TXIM_A {
211        match self.bits {
212            false => TXIM_A::MASKED,
213            true => TXIM_A::NOT_MASKED,
214        }
215    }
216    #[doc = "Checks if the value of the field is `MASKED`"]
217    #[inline(always)]
218    pub fn is_masked(&self) -> bool {
219        *self == TXIM_A::MASKED
220    }
221    #[doc = "Checks if the value of the field is `NOT_MASKED`"]
222    #[inline(always)]
223    pub fn is_not_masked(&self) -> bool {
224        *self == TXIM_A::NOT_MASKED
225    }
226}
227#[doc = "Field `TXIM` writer - Transmit FIFO interrupt mask"]
228pub type TXIM_W<'a, const O: u8> = crate::BitWriter<'a, u32, IMSC_SPEC, TXIM_A, O>;
229impl<'a, const O: u8> TXIM_W<'a, O> {
230    #[doc = "Transmit FIFO half empty or less condition interrupt is masked"]
231    #[inline(always)]
232    pub fn masked(self) -> &'a mut W {
233        self.variant(TXIM_A::MASKED)
234    }
235    #[doc = "Transmit FIFO half empty or less condition interrupt is not masked"]
236    #[inline(always)]
237    pub fn not_masked(self) -> &'a mut W {
238        self.variant(TXIM_A::NOT_MASKED)
239    }
240}
241impl R {
242    #[doc = "Bit 0 - Receive overrun interrupt mask"]
243    #[inline(always)]
244    pub fn rorim(&self) -> RORIM_R {
245        RORIM_R::new((self.bits & 1) != 0)
246    }
247    #[doc = "Bit 1 - Receive timeout interrupt mask"]
248    #[inline(always)]
249    pub fn rtim(&self) -> RTIM_R {
250        RTIM_R::new(((self.bits >> 1) & 1) != 0)
251    }
252    #[doc = "Bit 2 - Receive FIFO interrupt mask"]
253    #[inline(always)]
254    pub fn rxim(&self) -> RXIM_R {
255        RXIM_R::new(((self.bits >> 2) & 1) != 0)
256    }
257    #[doc = "Bit 3 - Transmit FIFO interrupt mask"]
258    #[inline(always)]
259    pub fn txim(&self) -> TXIM_R {
260        TXIM_R::new(((self.bits >> 3) & 1) != 0)
261    }
262}
263impl W {
264    #[doc = "Bit 0 - Receive overrun interrupt mask"]
265    #[inline(always)]
266    pub fn rorim(&mut self) -> RORIM_W<0> {
267        RORIM_W::new(self)
268    }
269    #[doc = "Bit 1 - Receive timeout interrupt mask"]
270    #[inline(always)]
271    pub fn rtim(&mut self) -> RTIM_W<1> {
272        RTIM_W::new(self)
273    }
274    #[doc = "Bit 2 - Receive FIFO interrupt mask"]
275    #[inline(always)]
276    pub fn rxim(&mut self) -> RXIM_W<2> {
277        RXIM_W::new(self)
278    }
279    #[doc = "Bit 3 - Transmit FIFO interrupt mask"]
280    #[inline(always)]
281    pub fn txim(&mut self) -> TXIM_W<3> {
282        TXIM_W::new(self)
283    }
284    #[doc = "Writes raw bits to the register."]
285    #[inline(always)]
286    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
287        self.0.bits(bits);
288        self
289    }
290}
291#[doc = "Interrupt mask set or clear register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [imsc](index.html) module"]
292pub struct IMSC_SPEC;
293impl crate::RegisterSpec for IMSC_SPEC {
294    type Ux = u32;
295}
296#[doc = "`read()` method returns [imsc::R](R) reader structure"]
297impl crate::Readable for IMSC_SPEC {
298    type Reader = R;
299}
300#[doc = "`write(|w| ..)` method takes [imsc::W](W) writer structure"]
301impl crate::Writable for IMSC_SPEC {
302    type Writer = W;
303}
304#[doc = "`reset()` method sets IMSC to value 0"]
305impl crate::Resettable for IMSC_SPEC {
306    #[inline(always)]
307    fn reset_value() -> Self::Ux {
308        0
309    }
310}
corstone300_pac/ssp0/imsc.rs

corstone300_pac/ssp0/
imsc.rs
