corstone300_pac/fpgaio/
misc.rs

1// Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
2//
3// SPDX-License-Identifier: MIT
4
5#[doc = "Register `MISC` reader"]
6pub struct R(crate::R<MISC_SPEC>);
7impl core::ops::Deref for R {
8    type Target = crate::R<MISC_SPEC>;
9    #[inline(always)]
10    fn deref(&self) -> &Self::Target {
11        &self.0
12    }
13}
14impl From<crate::R<MISC_SPEC>> for R {
15    #[inline(always)]
16    fn from(reader: crate::R<MISC_SPEC>) -> Self {
17        R(reader)
18    }
19}
20#[doc = "Register `MISC` writer"]
21pub struct W(crate::W<MISC_SPEC>);
22impl core::ops::Deref for W {
23    type Target = crate::W<MISC_SPEC>;
24    #[inline(always)]
25    fn deref(&self) -> &Self::Target {
26        &self.0
27    }
28}
29impl core::ops::DerefMut for W {
30    #[inline(always)]
31    fn deref_mut(&mut self) -> &mut Self::Target {
32        &mut self.0
33    }
34}
35impl From<crate::W<MISC_SPEC>> for W {
36    #[inline(always)]
37    fn from(writer: crate::W<MISC_SPEC>) -> Self {
38        W(writer)
39    }
40}
41#[doc = "Field `CLCD_CS` reader - "]
42pub type CLCD_CS_R = crate::BitReader<bool>;
43#[doc = "Field `CLCD_CS` writer - "]
44pub type CLCD_CS_W<'a, const O: u8> = crate::BitWriter<'a, u32, MISC_SPEC, bool, O>;
45#[doc = "Field `SPI_nSS` reader - "]
46pub type SPI_N_SS_R = crate::BitReader<bool>;
47#[doc = "Field `SPI_nSS` writer - "]
48pub type SPI_N_SS_W<'a, const O: u8> = crate::BitWriter<'a, u32, MISC_SPEC, bool, O>;
49#[doc = "Field `CLCD_RESET` reader - "]
50pub type CLCD_RESET_R = crate::BitReader<bool>;
51#[doc = "Field `CLCD_RESET` writer - "]
52pub type CLCD_RESET_W<'a, const O: u8> = crate::BitWriter<'a, u32, MISC_SPEC, bool, O>;
53#[doc = "Field `CLCD_RS` reader - "]
54pub type CLCD_RS_R = crate::BitReader<bool>;
55#[doc = "Field `CLCD_RS` writer - "]
56pub type CLCD_RS_W<'a, const O: u8> = crate::BitWriter<'a, u32, MISC_SPEC, bool, O>;
57#[doc = "Field `CLCD_RD` reader - "]
58pub type CLCD_RD_R = crate::BitReader<bool>;
59#[doc = "Field `CLCD_RD` writer - "]
60pub type CLCD_RD_W<'a, const O: u8> = crate::BitWriter<'a, u32, MISC_SPEC, bool, O>;
61#[doc = "Field `CLCD_BL_CTRL` reader - "]
62pub type CLCD_BL_CTRL_R = crate::BitReader<bool>;
63#[doc = "Field `CLCD_BL_CTRL` writer - "]
64pub type CLCD_BL_CTRL_W<'a, const O: u8> = crate::BitWriter<'a, u32, MISC_SPEC, bool, O>;
65#[doc = "Field `ADC_SPI_nCS` reader - "]
66pub type ADC_SPI_N_CS_R = crate::BitReader<bool>;
67#[doc = "Field `ADC_SPI_nCS` writer - "]
68pub type ADC_SPI_N_CS_W<'a, const O: u8> = crate::BitWriter<'a, u32, MISC_SPEC, bool, O>;
69#[doc = "Field `SHIELD0_SPI_nCS` reader - "]
70pub type SHIELD0_SPI_N_CS_R = crate::BitReader<bool>;
71#[doc = "Field `SHIELD0_SPI_nCS` writer - "]
72pub type SHIELD0_SPI_N_CS_W<'a, const O: u8> = crate::BitWriter<'a, u32, MISC_SPEC, bool, O>;
73#[doc = "Field `SHIELD1_SPI_nCS` reader - "]
74pub type SHIELD1_SPI_N_CS_R = crate::BitReader<bool>;
75#[doc = "Field `SHIELD1_SPI_nCS` writer - "]
76pub type SHIELD1_SPI_N_CS_W<'a, const O: u8> = crate::BitWriter<'a, u32, MISC_SPEC, bool, O>;
77impl R {
78    #[doc = "Bit 0"]
79    #[inline(always)]
80    pub fn clcd_cs(&self) -> CLCD_CS_R {
81        CLCD_CS_R::new((self.bits & 1) != 0)
82    }
83    #[doc = "Bit 1"]
84    #[inline(always)]
85    pub fn spi_n_ss(&self) -> SPI_N_SS_R {
86        SPI_N_SS_R::new(((self.bits >> 1) & 1) != 0)
87    }
88    #[doc = "Bit 3"]
89    #[inline(always)]
90    pub fn clcd_reset(&self) -> CLCD_RESET_R {
91        CLCD_RESET_R::new(((self.bits >> 3) & 1) != 0)
92    }
93    #[doc = "Bit 4"]
94    #[inline(always)]
95    pub fn clcd_rs(&self) -> CLCD_RS_R {
96        CLCD_RS_R::new(((self.bits >> 4) & 1) != 0)
97    }
98    #[doc = "Bit 5"]
99    #[inline(always)]
100    pub fn clcd_rd(&self) -> CLCD_RD_R {
101        CLCD_RD_R::new(((self.bits >> 5) & 1) != 0)
102    }
103    #[doc = "Bit 6"]
104    #[inline(always)]
105    pub fn clcd_bl_ctrl(&self) -> CLCD_BL_CTRL_R {
106        CLCD_BL_CTRL_R::new(((self.bits >> 6) & 1) != 0)
107    }
108    #[doc = "Bit 7"]
109    #[inline(always)]
110    pub fn adc_spi_n_cs(&self) -> ADC_SPI_N_CS_R {
111        ADC_SPI_N_CS_R::new(((self.bits >> 7) & 1) != 0)
112    }
113    #[doc = "Bit 8"]
114    #[inline(always)]
115    pub fn shield0_spi_n_cs(&self) -> SHIELD0_SPI_N_CS_R {
116        SHIELD0_SPI_N_CS_R::new(((self.bits >> 8) & 1) != 0)
117    }
118    #[doc = "Bit 9"]
119    #[inline(always)]
120    pub fn shield1_spi_n_cs(&self) -> SHIELD1_SPI_N_CS_R {
121        SHIELD1_SPI_N_CS_R::new(((self.bits >> 9) & 1) != 0)
122    }
123}
124impl W {
125    #[doc = "Bit 0"]
126    #[inline(always)]
127    pub fn clcd_cs(&mut self) -> CLCD_CS_W<0> {
128        CLCD_CS_W::new(self)
129    }
130    #[doc = "Bit 1"]
131    #[inline(always)]
132    pub fn spi_n_ss(&mut self) -> SPI_N_SS_W<1> {
133        SPI_N_SS_W::new(self)
134    }
135    #[doc = "Bit 3"]
136    #[inline(always)]
137    pub fn clcd_reset(&mut self) -> CLCD_RESET_W<3> {
138        CLCD_RESET_W::new(self)
139    }
140    #[doc = "Bit 4"]
141    #[inline(always)]
142    pub fn clcd_rs(&mut self) -> CLCD_RS_W<4> {
143        CLCD_RS_W::new(self)
144    }
145    #[doc = "Bit 5"]
146    #[inline(always)]
147    pub fn clcd_rd(&mut self) -> CLCD_RD_W<5> {
148        CLCD_RD_W::new(self)
149    }
150    #[doc = "Bit 6"]
151    #[inline(always)]
152    pub fn clcd_bl_ctrl(&mut self) -> CLCD_BL_CTRL_W<6> {
153        CLCD_BL_CTRL_W::new(self)
154    }
155    #[doc = "Bit 7"]
156    #[inline(always)]
157    pub fn adc_spi_n_cs(&mut self) -> ADC_SPI_N_CS_W<7> {
158        ADC_SPI_N_CS_W::new(self)
159    }
160    #[doc = "Bit 8"]
161    #[inline(always)]
162    pub fn shield0_spi_n_cs(&mut self) -> SHIELD0_SPI_N_CS_W<8> {
163        SHIELD0_SPI_N_CS_W::new(self)
164    }
165    #[doc = "Bit 9"]
166    #[inline(always)]
167    pub fn shield1_spi_n_cs(&mut self) -> SHIELD1_SPI_N_CS_W<9> {
168        SHIELD1_SPI_N_CS_W::new(self)
169    }
170    #[doc = "Writes raw bits to the register."]
171    #[inline(always)]
172    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
173        self.0.bits(bits);
174        self
175    }
176}
177#[doc = "Misc. Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [misc](index.html) module"]
178pub struct MISC_SPEC;
179impl crate::RegisterSpec for MISC_SPEC {
180    type Ux = u32;
181}
182#[doc = "`read()` method returns [misc::R](R) reader structure"]
183impl crate::Readable for MISC_SPEC {
184    type Reader = R;
185}
186#[doc = "`write(|w| ..)` method takes [misc::W](W) writer structure"]
187impl crate::Writable for MISC_SPEC {
188    type Writer = W;
189}
190#[doc = "`reset()` method sets MISC to value 0"]
191impl crate::Resettable for MISC_SPEC {
192    #[inline(always)]
193    fn reset_value() -> Self::Ux {
194        0
195    }
196}
corstone300_pac/fpgaio/misc.rs

corstone300_pac/fpgaio/
misc.rs
