corstone300_pac/ethernet/
irq_cfg.rs

1// Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
2//
3// SPDX-License-Identifier: MIT
4
5#[doc = "Register `IRQ_CFG` reader"]
6pub struct R(crate::R<IRQ_CFG_SPEC>);
7impl core::ops::Deref for R {
8    type Target = crate::R<IRQ_CFG_SPEC>;
9    #[inline(always)]
10    fn deref(&self) -> &Self::Target {
11        &self.0
12    }
13}
14impl From<crate::R<IRQ_CFG_SPEC>> for R {
15    #[inline(always)]
16    fn from(reader: crate::R<IRQ_CFG_SPEC>) -> Self {
17        R(reader)
18    }
19}
20#[doc = "Register `IRQ_CFG` writer"]
21pub struct W(crate::W<IRQ_CFG_SPEC>);
22impl core::ops::Deref for W {
23    type Target = crate::W<IRQ_CFG_SPEC>;
24    #[inline(always)]
25    fn deref(&self) -> &Self::Target {
26        &self.0
27    }
28}
29impl core::ops::DerefMut for W {
30    #[inline(always)]
31    fn deref_mut(&mut self) -> &mut Self::Target {
32        &mut self.0
33    }
34}
35impl From<crate::W<IRQ_CFG_SPEC>> for W {
36    #[inline(always)]
37    fn from(writer: crate::W<IRQ_CFG_SPEC>) -> Self {
38        W(writer)
39    }
40}
41#[doc = "Field `IRQ_TYPE` reader - IRQ Buffer Type"]
42pub type IRQ_TYPE_R = crate::BitReader<bool>;
43#[doc = "Field `IRQ_TYPE` writer - IRQ Buffer Type"]
44pub type IRQ_TYPE_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRQ_CFG_SPEC, bool, O>;
45#[doc = "Field `IRQ_POL` reader - IRQ Polarity"]
46pub type IRQ_POL_R = crate::BitReader<bool>;
47#[doc = "Field `IRQ_POL` writer - IRQ Polarity"]
48pub type IRQ_POL_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRQ_CFG_SPEC, bool, O>;
49#[doc = "Field `IRQ_EN` reader - IRQ Enable"]
50pub type IRQ_EN_R = crate::BitReader<bool>;
51#[doc = "Field `IRQ_EN` writer - IRQ Enable"]
52pub type IRQ_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, IRQ_CFG_SPEC, bool, O>;
53#[doc = "Field `IRQ_INT` reader - Master Interrupt"]
54pub type IRQ_INT_R = crate::BitReader<bool>;
55#[doc = "Field `INT_DEAS_STS` reader - Interrupt Deassertion Status"]
56pub type INT_DEAS_STS_R = crate::BitReader<bool>;
57#[doc = "Field `INT_DEAS_CLR` reader - Interrupt Deassertion Interval Clear"]
58pub type INT_DEAS_CLR_R = crate::BitReader<bool>;
59#[doc = "Field `INT_DEAS` reader - Interrupt Deassertion Interval"]
60pub type INT_DEAS_R = crate::FieldReader<u8, u8>;
61#[doc = "Field `INT_DEAS` writer - Interrupt Deassertion Interval"]
62pub type INT_DEAS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, IRQ_CFG_SPEC, u8, u8, 8, O>;
63impl R {
64    #[doc = "Bit 0 - IRQ Buffer Type"]
65    #[inline(always)]
66    pub fn irq_type(&self) -> IRQ_TYPE_R {
67        IRQ_TYPE_R::new((self.bits & 1) != 0)
68    }
69    #[doc = "Bit 4 - IRQ Polarity"]
70    #[inline(always)]
71    pub fn irq_pol(&self) -> IRQ_POL_R {
72        IRQ_POL_R::new(((self.bits >> 4) & 1) != 0)
73    }
74    #[doc = "Bit 8 - IRQ Enable"]
75    #[inline(always)]
76    pub fn irq_en(&self) -> IRQ_EN_R {
77        IRQ_EN_R::new(((self.bits >> 8) & 1) != 0)
78    }
79    #[doc = "Bit 12 - Master Interrupt"]
80    #[inline(always)]
81    pub fn irq_int(&self) -> IRQ_INT_R {
82        IRQ_INT_R::new(((self.bits >> 12) & 1) != 0)
83    }
84    #[doc = "Bit 13 - Interrupt Deassertion Status"]
85    #[inline(always)]
86    pub fn int_deas_sts(&self) -> INT_DEAS_STS_R {
87        INT_DEAS_STS_R::new(((self.bits >> 13) & 1) != 0)
88    }
89    #[doc = "Bit 14 - Interrupt Deassertion Interval Clear"]
90    #[inline(always)]
91    pub fn int_deas_clr(&self) -> INT_DEAS_CLR_R {
92        INT_DEAS_CLR_R::new(((self.bits >> 14) & 1) != 0)
93    }
94    #[doc = "Bits 24:31 - Interrupt Deassertion Interval"]
95    #[inline(always)]
96    pub fn int_deas(&self) -> INT_DEAS_R {
97        INT_DEAS_R::new(((self.bits >> 24) & 0xff) as u8)
98    }
99}
100impl W {
101    #[doc = "Bit 0 - IRQ Buffer Type"]
102    #[inline(always)]
103    pub fn irq_type(&mut self) -> IRQ_TYPE_W<0> {
104        IRQ_TYPE_W::new(self)
105    }
106    #[doc = "Bit 4 - IRQ Polarity"]
107    #[inline(always)]
108    pub fn irq_pol(&mut self) -> IRQ_POL_W<4> {
109        IRQ_POL_W::new(self)
110    }
111    #[doc = "Bit 8 - IRQ Enable"]
112    #[inline(always)]
113    pub fn irq_en(&mut self) -> IRQ_EN_W<8> {
114        IRQ_EN_W::new(self)
115    }
116    #[doc = "Bits 24:31 - Interrupt Deassertion Interval"]
117    #[inline(always)]
118    pub fn int_deas(&mut self) -> INT_DEAS_W<24> {
119        INT_DEAS_W::new(self)
120    }
121    #[doc = "Writes raw bits to the register."]
122    #[inline(always)]
123    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
124        self.0.bits(bits);
125        self
126    }
127}
128#[doc = "Main Interrupt Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_cfg](index.html) module"]
129pub struct IRQ_CFG_SPEC;
130impl crate::RegisterSpec for IRQ_CFG_SPEC {
131    type Ux = u32;
132}
133#[doc = "`read()` method returns [irq_cfg::R](R) reader structure"]
134impl crate::Readable for IRQ_CFG_SPEC {
135    type Reader = R;
136}
137#[doc = "`write(|w| ..)` method takes [irq_cfg::W](W) writer structure"]
138impl crate::Writable for IRQ_CFG_SPEC {
139    type Writer = W;
140}
141#[doc = "`reset()` method sets IRQ_CFG to value 0"]
142impl crate::Resettable for IRQ_CFG_SPEC {
143    #[inline(always)]
144    fn reset_value() -> Self::Ux {
145        0
146    }
147}
corstone300_pac/ethernet/irq_cfg.rs

corstone300_pac/ethernet/
irq_cfg.rs
