corstone300_pac/ethernet/
hw_cfg.rs

1// Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
2//
3// SPDX-License-Identifier: MIT
4
5#[doc = "Register `HW_CFG` reader"]
6pub struct R(crate::R<HW_CFG_SPEC>);
7impl core::ops::Deref for R {
8    type Target = crate::R<HW_CFG_SPEC>;
9    #[inline(always)]
10    fn deref(&self) -> &Self::Target {
11        &self.0
12    }
13}
14impl From<crate::R<HW_CFG_SPEC>> for R {
15    #[inline(always)]
16    fn from(reader: crate::R<HW_CFG_SPEC>) -> Self {
17        R(reader)
18    }
19}
20#[doc = "Register `HW_CFG` writer"]
21pub struct W(crate::W<HW_CFG_SPEC>);
22impl core::ops::Deref for W {
23    type Target = crate::W<HW_CFG_SPEC>;
24    #[inline(always)]
25    fn deref(&self) -> &Self::Target {
26        &self.0
27    }
28}
29impl core::ops::DerefMut for W {
30    #[inline(always)]
31    fn deref_mut(&mut self) -> &mut Self::Target {
32        &mut self.0
33    }
34}
35impl From<crate::W<HW_CFG_SPEC>> for W {
36    #[inline(always)]
37    fn from(writer: crate::W<HW_CFG_SPEC>) -> Self {
38        W(writer)
39    }
40}
41#[doc = "Field `SRST` reader - Soft Reset"]
42pub type SRST_R = crate::BitReader<bool>;
43#[doc = "Field `SRST` writer - Soft Reset"]
44pub type SRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, HW_CFG_SPEC, bool, O>;
45#[doc = "Field `SRST_TO` reader - Soft Reset Timeout"]
46pub type SRST_TO_R = crate::BitReader<bool>;
47#[doc = "Field `TX_FIF_SZ` reader - TX FIFO Size"]
48pub type TX_FIF_SZ_R = crate::FieldReader<u8, u8>;
49#[doc = "Field `TX_FIF_SZ` writer - TX FIFO Size"]
50pub type TX_FIF_SZ_W<'a, const O: u8> = crate::FieldWriter<'a, u32, HW_CFG_SPEC, u8, u8, 4, O>;
51#[doc = "Field `MBO` reader - Must Be One"]
52pub type MBO_R = crate::BitReader<MBO_A>;
53#[doc = "Must Be One\n\nValue on reset: 0"]
54#[derive(Clone, Copy, Debug, PartialEq, Eq)]
55pub enum MBO_A {
56    #[doc = "1: `1`"]
57    ONE = 1,
58}
59impl From<MBO_A> for bool {
60    #[inline(always)]
61    fn from(variant: MBO_A) -> Self {
62        variant as u8 != 0
63    }
64}
65impl MBO_R {
66    #[doc = "Get enumerated values variant"]
67    #[inline(always)]
68    pub fn variant(&self) -> Option<MBO_A> {
69        match self.bits {
70            true => Some(MBO_A::ONE),
71            _ => None,
72        }
73    }
74    #[doc = "Checks if the value of the field is `ONE`"]
75    #[inline(always)]
76    pub fn is_one(&self) -> bool {
77        *self == MBO_A::ONE
78    }
79}
80#[doc = "Field `MBO` writer - Must Be One"]
81pub type MBO_W<'a, const O: u8> = crate::BitWriter<'a, u32, HW_CFG_SPEC, MBO_A, O>;
82impl<'a, const O: u8> MBO_W<'a, O> {
83    #[doc = "`1`"]
84    #[inline(always)]
85    pub fn one(self) -> &'a mut W {
86        self.variant(MBO_A::ONE)
87    }
88}
89#[doc = "Field `AMDIX_EN` reader - AMDIX_EN Strap state"]
90pub type AMDIX_EN_R = crate::BitReader<bool>;
91#[doc = "Field `AMDIX_EN` writer - AMDIX_EN Strap state"]
92pub type AMDIX_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, HW_CFG_SPEC, bool, O>;
93#[doc = "Field `FSELEND` reader - Direct FIFO Access Endian Ordering"]
94pub type FSELEND_R = crate::BitReader<FSELEND_A>;
95#[doc = "Direct FIFO Access Endian Ordering\n\nValue on reset: 0"]
96#[derive(Clone, Copy, Debug, PartialEq, Eq)]
97pub enum FSELEND_A {
98    #[doc = "0: Little Endian"]
99    LE = 0,
100    #[doc = "1: Big Endian"]
101    BE = 1,
102}
103impl From<FSELEND_A> for bool {
104    #[inline(always)]
105    fn from(variant: FSELEND_A) -> Self {
106        variant as u8 != 0
107    }
108}
109impl FSELEND_R {
110    #[doc = "Get enumerated values variant"]
111    #[inline(always)]
112    pub fn variant(&self) -> FSELEND_A {
113        match self.bits {
114            false => FSELEND_A::LE,
115            true => FSELEND_A::BE,
116        }
117    }
118    #[doc = "Checks if the value of the field is `LE`"]
119    #[inline(always)]
120    pub fn is_le(&self) -> bool {
121        *self == FSELEND_A::LE
122    }
123    #[doc = "Checks if the value of the field is `BE`"]
124    #[inline(always)]
125    pub fn is_be(&self) -> bool {
126        *self == FSELEND_A::BE
127    }
128}
129#[doc = "Field `FSELEND` writer - Direct FIFO Access Endian Ordering"]
130pub type FSELEND_W<'a, const O: u8> = crate::BitWriter<'a, u32, HW_CFG_SPEC, FSELEND_A, O>;
131impl<'a, const O: u8> FSELEND_W<'a, O> {
132    #[doc = "Little Endian"]
133    #[inline(always)]
134    pub fn le(self) -> &'a mut W {
135        self.variant(FSELEND_A::LE)
136    }
137    #[doc = "Big Endian"]
138    #[inline(always)]
139    pub fn be(self) -> &'a mut W {
140        self.variant(FSELEND_A::BE)
141    }
142}
143#[doc = "Field `FPORTEND` reader - FIFO Port Endian Ordering"]
144pub type FPORTEND_R = crate::BitReader<FPORTEND_A>;
145#[doc = "FIFO Port Endian Ordering\n\nValue on reset: 0"]
146#[derive(Clone, Copy, Debug, PartialEq, Eq)]
147pub enum FPORTEND_A {
148    #[doc = "0: Little Endian"]
149    LE = 0,
150    #[doc = "1: Big Endian"]
151    BE = 1,
152}
153impl From<FPORTEND_A> for bool {
154    #[inline(always)]
155    fn from(variant: FPORTEND_A) -> Self {
156        variant as u8 != 0
157    }
158}
159impl FPORTEND_R {
160    #[doc = "Get enumerated values variant"]
161    #[inline(always)]
162    pub fn variant(&self) -> FPORTEND_A {
163        match self.bits {
164            false => FPORTEND_A::LE,
165            true => FPORTEND_A::BE,
166        }
167    }
168    #[doc = "Checks if the value of the field is `LE`"]
169    #[inline(always)]
170    pub fn is_le(&self) -> bool {
171        *self == FPORTEND_A::LE
172    }
173    #[doc = "Checks if the value of the field is `BE`"]
174    #[inline(always)]
175    pub fn is_be(&self) -> bool {
176        *self == FPORTEND_A::BE
177    }
178}
179#[doc = "Field `FPORTEND` writer - FIFO Port Endian Ordering"]
180pub type FPORTEND_W<'a, const O: u8> = crate::BitWriter<'a, u32, HW_CFG_SPEC, FPORTEND_A, O>;
181impl<'a, const O: u8> FPORTEND_W<'a, O> {
182    #[doc = "Little Endian"]
183    #[inline(always)]
184    pub fn le(self) -> &'a mut W {
185        self.variant(FPORTEND_A::LE)
186    }
187    #[doc = "Big Endian"]
188    #[inline(always)]
189    pub fn be(self) -> &'a mut W {
190        self.variant(FPORTEND_A::BE)
191    }
192}
193impl R {
194    #[doc = "Bit 0 - Soft Reset"]
195    #[inline(always)]
196    pub fn srst(&self) -> SRST_R {
197        SRST_R::new((self.bits & 1) != 0)
198    }
199    #[doc = "Bit 1 - Soft Reset Timeout"]
200    #[inline(always)]
201    pub fn srst_to(&self) -> SRST_TO_R {
202        SRST_TO_R::new(((self.bits >> 1) & 1) != 0)
203    }
204    #[doc = "Bits 16:19 - TX FIFO Size"]
205    #[inline(always)]
206    pub fn tx_fif_sz(&self) -> TX_FIF_SZ_R {
207        TX_FIF_SZ_R::new(((self.bits >> 16) & 0x0f) as u8)
208    }
209    #[doc = "Bit 20 - Must Be One"]
210    #[inline(always)]
211    pub fn mbo(&self) -> MBO_R {
212        MBO_R::new(((self.bits >> 20) & 1) != 0)
213    }
214    #[doc = "Bit 24 - AMDIX_EN Strap state"]
215    #[inline(always)]
216    pub fn amdix_en(&self) -> AMDIX_EN_R {
217        AMDIX_EN_R::new(((self.bits >> 24) & 1) != 0)
218    }
219    #[doc = "Bit 28 - Direct FIFO Access Endian Ordering"]
220    #[inline(always)]
221    pub fn fselend(&self) -> FSELEND_R {
222        FSELEND_R::new(((self.bits >> 28) & 1) != 0)
223    }
224    #[doc = "Bit 29 - FIFO Port Endian Ordering"]
225    #[inline(always)]
226    pub fn fportend(&self) -> FPORTEND_R {
227        FPORTEND_R::new(((self.bits >> 29) & 1) != 0)
228    }
229}
230impl W {
231    #[doc = "Bit 0 - Soft Reset"]
232    #[inline(always)]
233    pub fn srst(&mut self) -> SRST_W<0> {
234        SRST_W::new(self)
235    }
236    #[doc = "Bits 16:19 - TX FIFO Size"]
237    #[inline(always)]
238    pub fn tx_fif_sz(&mut self) -> TX_FIF_SZ_W<16> {
239        TX_FIF_SZ_W::new(self)
240    }
241    #[doc = "Bit 20 - Must Be One"]
242    #[inline(always)]
243    pub fn mbo(&mut self) -> MBO_W<20> {
244        MBO_W::new(self)
245    }
246    #[doc = "Bit 24 - AMDIX_EN Strap state"]
247    #[inline(always)]
248    pub fn amdix_en(&mut self) -> AMDIX_EN_W<24> {
249        AMDIX_EN_W::new(self)
250    }
251    #[doc = "Bit 28 - Direct FIFO Access Endian Ordering"]
252    #[inline(always)]
253    pub fn fselend(&mut self) -> FSELEND_W<28> {
254        FSELEND_W::new(self)
255    }
256    #[doc = "Bit 29 - FIFO Port Endian Ordering"]
257    #[inline(always)]
258    pub fn fportend(&mut self) -> FPORTEND_W<29> {
259        FPORTEND_W::new(self)
260    }
261    #[doc = "Writes raw bits to the register."]
262    #[inline(always)]
263    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
264        self.0.bits(bits);
265        self
266    }
267}
268#[doc = "Hardware Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hw_cfg](index.html) module"]
269pub struct HW_CFG_SPEC;
270impl crate::RegisterSpec for HW_CFG_SPEC {
271    type Ux = u32;
272}
273#[doc = "`read()` method returns [hw_cfg::R](R) reader structure"]
274impl crate::Readable for HW_CFG_SPEC {
275    type Reader = R;
276}
277#[doc = "`write(|w| ..)` method takes [hw_cfg::W](W) writer structure"]
278impl crate::Writable for HW_CFG_SPEC {
279    type Writer = W;
280}
281#[doc = "`reset()` method sets HW_CFG to value 0x0005_0000"]
282impl crate::Resettable for HW_CFG_SPEC {
283    #[inline(always)]
284    fn reset_value() -> Self::Ux {
285        0x0005_0000
286    }
287}
corstone300_pac/ethernet/hw_cfg.rs

corstone300_pac/ethernet/
hw_cfg.rs
