corstone300_pac/syscontrol/
scsecctrl.rs

1// Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
2//
3// SPDX-License-Identifier: MIT
4
5#[doc = "Register `SCSECCTRL` reader"]
6pub struct R(crate::R<SCSECCTRL_SPEC>);
7impl core::ops::Deref for R {
8    type Target = crate::R<SCSECCTRL_SPEC>;
9    #[inline(always)]
10    fn deref(&self) -> &Self::Target {
11        &self.0
12    }
13}
14impl From<crate::R<SCSECCTRL_SPEC>> for R {
15    #[inline(always)]
16    fn from(reader: crate::R<SCSECCTRL_SPEC>) -> Self {
17        R(reader)
18    }
19}
20#[doc = "Register `SCSECCTRL` writer"]
21pub struct W(crate::W<SCSECCTRL_SPEC>);
22impl core::ops::Deref for W {
23    type Target = crate::W<SCSECCTRL_SPEC>;
24    #[inline(always)]
25    fn deref(&self) -> &Self::Target {
26        &self.0
27    }
28}
29impl core::ops::DerefMut for W {
30    #[inline(always)]
31    fn deref_mut(&mut self) -> &mut Self::Target {
32        &mut self.0
33    }
34}
35impl From<crate::W<SCSECCTRL_SPEC>> for W {
36    #[inline(always)]
37    fn from(writer: crate::W<SCSECCTRL_SPEC>) -> Self {
38        W(writer)
39    }
40}
41#[doc = "Field `SCSECCFGLOCK` reader - Control to disable writes to security-related control registers in this register block"]
42pub type SCSECCFGLOCK_R = crate::BitReader<SCSECCFGLOCK_A>;
43#[doc = "Control to disable writes to security-related control registers in this register block\n\nValue on reset: 0"]
44#[derive(Clone, Copy, Debug, PartialEq, Eq)]
45pub enum SCSECCFGLOCK_A {
46    #[doc = "1: control to disable writes to security-related control registers in this register block"]
47    DISABLE = 1,
48    #[doc = "0: control to enable writes to security-related control registers in this register block"]
49    ENABLE = 0,
50}
51impl From<SCSECCFGLOCK_A> for bool {
52    #[inline(always)]
53    fn from(variant: SCSECCFGLOCK_A) -> Self {
54        variant as u8 != 0
55    }
56}
57impl SCSECCFGLOCK_R {
58    #[doc = "Get enumerated values variant"]
59    #[inline(always)]
60    pub fn variant(&self) -> SCSECCFGLOCK_A {
61        match self.bits {
62            true => SCSECCFGLOCK_A::DISABLE,
63            false => SCSECCFGLOCK_A::ENABLE,
64        }
65    }
66    #[doc = "Checks if the value of the field is `DISABLE`"]
67    #[inline(always)]
68    pub fn is_disable(&self) -> bool {
69        *self == SCSECCFGLOCK_A::DISABLE
70    }
71    #[doc = "Checks if the value of the field is `ENABLE`"]
72    #[inline(always)]
73    pub fn is_enable(&self) -> bool {
74        *self == SCSECCFGLOCK_A::ENABLE
75    }
76}
77#[doc = "Field `SCSECCFGLOCK` writer - Control to disable writes to security-related control registers in this register block"]
78pub type SCSECCFGLOCK_W<'a, const O: u8> =
79    crate::BitWriter<'a, u32, SCSECCTRL_SPEC, SCSECCFGLOCK_A, O>;
80impl<'a, const O: u8> SCSECCFGLOCK_W<'a, O> {
81    #[doc = "control to disable writes to security-related control registers in this register block"]
82    #[inline(always)]
83    pub fn disable(self) -> &'a mut W {
84        self.variant(SCSECCFGLOCK_A::DISABLE)
85    }
86    #[doc = "control to enable writes to security-related control registers in this register block"]
87    #[inline(always)]
88    pub fn enable(self) -> &'a mut W {
89        self.variant(SCSECCFGLOCK_A::ENABLE)
90    }
91}
92impl R {
93    #[doc = "Bit 2 - Control to disable writes to security-related control registers in this register block"]
94    #[inline(always)]
95    pub fn scseccfglock(&self) -> SCSECCFGLOCK_R {
96        SCSECCFGLOCK_R::new(((self.bits >> 2) & 1) != 0)
97    }
98}
99impl W {
100    #[doc = "Bit 2 - Control to disable writes to security-related control registers in this register block"]
101    #[inline(always)]
102    pub fn scseccfglock(&mut self) -> SCSECCFGLOCK_W<2> {
103        SCSECCFGLOCK_W::new(self)
104    }
105    #[doc = "Writes raw bits to the register."]
106    #[inline(always)]
107    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
108        self.0.bits(bits);
109        self
110    }
111}
112#[doc = "System Security Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scsecctrl](index.html) module"]
113pub struct SCSECCTRL_SPEC;
114impl crate::RegisterSpec for SCSECCTRL_SPEC {
115    type Ux = u32;
116}
117#[doc = "`read()` method returns [scsecctrl::R](R) reader structure"]
118impl crate::Readable for SCSECCTRL_SPEC {
119    type Reader = R;
120}
121#[doc = "`write(|w| ..)` method takes [scsecctrl::W](W) writer structure"]
122impl crate::Writable for SCSECCTRL_SPEC {
123    type Writer = W;
124}
125#[doc = "`reset()` method sets SCSECCTRL to value 0"]
126impl crate::Resettable for SCSECCTRL_SPEC {
127    #[inline(always)]
128    fn reset_value() -> Self::Ux {
129        0
130    }
131}
corstone300_pac/syscontrol/scsecctrl.rs

corstone300_pac/syscontrol/
scsecctrl.rs
