corstone300_pac/syscontrol/
initsvrtor0.rs

1// Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
2//
3// SPDX-License-Identifier: MIT
4
5#[doc = "Register `INITSVRTOR0` reader"]
6pub struct R(crate::R<INITSVRTOR0_SPEC>);
7impl core::ops::Deref for R {
8    type Target = crate::R<INITSVRTOR0_SPEC>;
9    #[inline(always)]
10    fn deref(&self) -> &Self::Target {
11        &self.0
12    }
13}
14impl From<crate::R<INITSVRTOR0_SPEC>> for R {
15    #[inline(always)]
16    fn from(reader: crate::R<INITSVRTOR0_SPEC>) -> Self {
17        R(reader)
18    }
19}
20#[doc = "Register `INITSVRTOR0` writer"]
21pub struct W(crate::W<INITSVRTOR0_SPEC>);
22impl core::ops::Deref for W {
23    type Target = crate::W<INITSVRTOR0_SPEC>;
24    #[inline(always)]
25    fn deref(&self) -> &Self::Target {
26        &self.0
27    }
28}
29impl core::ops::DerefMut for W {
30    #[inline(always)]
31    fn deref_mut(&mut self) -> &mut Self::Target {
32        &mut self.0
33    }
34}
35impl From<crate::W<INITSVRTOR0_SPEC>> for W {
36    #[inline(always)]
37    fn from(writer: crate::W<INITSVRTOR0_SPEC>) -> Self {
38        W(writer)
39    }
40}
41#[doc = "Field `INITSVTOR0LOCK` writer - Lock INITSVTOR0. When set to 1, will stop any further writes to INITSVTOR0 and INITSVTOR0LOCK fields. Cleared only by Warm reset."]
42pub type INITSVTOR0LOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, INITSVRTOR0_SPEC, bool, O>;
43#[doc = "Field `INITSVTOR0` reader - Default Secure Vector table offset at reset for CPU 0"]
44pub type INITSVTOR0_R = crate::FieldReader<u32, u32>;
45#[doc = "Field `INITSVTOR0` writer - Default Secure Vector table offset at reset for CPU 0"]
46pub type INITSVTOR0_W<'a, const O: u8> =
47    crate::FieldWriter<'a, u32, INITSVRTOR0_SPEC, u32, u32, 25, O>;
48impl R {
49    #[doc = "Bits 7:31 - Default Secure Vector table offset at reset for CPU 0"]
50    #[inline(always)]
51    pub fn initsvtor0(&self) -> INITSVTOR0_R {
52        INITSVTOR0_R::new(((self.bits >> 7) & 0x01ff_ffff) as u32)
53    }
54}
55impl W {
56    #[doc = "Bit 0 - Lock INITSVTOR0. When set to 1, will stop any further writes to INITSVTOR0 and INITSVTOR0LOCK fields. Cleared only by Warm reset."]
57    #[inline(always)]
58    pub fn initsvtor0lock(&mut self) -> INITSVTOR0LOCK_W<0> {
59        INITSVTOR0LOCK_W::new(self)
60    }
61    #[doc = "Bits 7:31 - Default Secure Vector table offset at reset for CPU 0"]
62    #[inline(always)]
63    pub fn initsvtor0(&mut self) -> INITSVTOR0_W<7> {
64        INITSVTOR0_W::new(self)
65    }
66    #[doc = "Writes raw bits to the register."]
67    #[inline(always)]
68    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
69        self.0.bits(bits);
70        self
71    }
72}
73#[doc = "Initial Secure Reset Vector Register For CPU 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [initsvrtor0](index.html) module"]
74pub struct INITSVRTOR0_SPEC;
75impl crate::RegisterSpec for INITSVRTOR0_SPEC {
76    type Ux = u32;
77}
78#[doc = "`read()` method returns [initsvrtor0::R](R) reader structure"]
79impl crate::Readable for INITSVRTOR0_SPEC {
80    type Reader = R;
81}
82#[doc = "`write(|w| ..)` method takes [initsvrtor0::W](W) writer structure"]
83impl crate::Writable for INITSVRTOR0_SPEC {
84    type Writer = W;
85}
86#[doc = "`reset()` method sets INITSVRTOR0 to value 0"]
87impl crate::Resettable for INITSVRTOR0_SPEC {
88    #[inline(always)]
89    fn reset_value() -> Self::Ux {
90        0
91    }
92}
corstone300_pac/syscontrol/initsvrtor0.rs

corstone300_pac/syscontrol/
initsvrtor0.rs
