corstone300_pac/ssp0/
tcr.rs1#[doc = "Register `TCR` reader"]
6pub struct R(crate::R<TCR_SPEC>);
7impl core::ops::Deref for R {
8 type Target = crate::R<TCR_SPEC>;
9 #[inline(always)]
10 fn deref(&self) -> &Self::Target {
11 &self.0
12 }
13}
14impl From<crate::R<TCR_SPEC>> for R {
15 #[inline(always)]
16 fn from(reader: crate::R<TCR_SPEC>) -> Self {
17 R(reader)
18 }
19}
20#[doc = "Register `TCR` writer"]
21pub struct W(crate::W<TCR_SPEC>);
22impl core::ops::Deref for W {
23 type Target = crate::W<TCR_SPEC>;
24 #[inline(always)]
25 fn deref(&self) -> &Self::Target {
26 &self.0
27 }
28}
29impl core::ops::DerefMut for W {
30 #[inline(always)]
31 fn deref_mut(&mut self) -> &mut Self::Target {
32 &mut self.0
33 }
34}
35impl From<crate::W<TCR_SPEC>> for W {
36 #[inline(always)]
37 fn from(writer: crate::W<TCR_SPEC>) -> Self {
38 W(writer)
39 }
40}
41#[doc = "Field `ITEN` reader - Integration test enable"]
42pub type ITEN_R = crate::BitReader<ITEN_A>;
43#[doc = "Integration test enable\n\nValue on reset: 0"]
44#[derive(Clone, Copy, Debug, PartialEq, Eq)]
45pub enum ITEN_A {
46 #[doc = "0: Normal mode"]
47 DISABLED = 0,
48 #[doc = "1: The PrimeCell SSP is placed in integration test mode."]
49 ENABLED = 1,
50}
51impl From<ITEN_A> for bool {
52 #[inline(always)]
53 fn from(variant: ITEN_A) -> Self {
54 variant as u8 != 0
55 }
56}
57impl ITEN_R {
58 #[doc = "Get enumerated values variant"]
59 #[inline(always)]
60 pub fn variant(&self) -> ITEN_A {
61 match self.bits {
62 false => ITEN_A::DISABLED,
63 true => ITEN_A::ENABLED,
64 }
65 }
66 #[doc = "Checks if the value of the field is `DISABLED`"]
67 #[inline(always)]
68 pub fn is_disabled(&self) -> bool {
69 *self == ITEN_A::DISABLED
70 }
71 #[doc = "Checks if the value of the field is `ENABLED`"]
72 #[inline(always)]
73 pub fn is_enabled(&self) -> bool {
74 *self == ITEN_A::ENABLED
75 }
76}
77#[doc = "Field `ITEN` writer - Integration test enable"]
78pub type ITEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, TCR_SPEC, ITEN_A, O>;
79impl<'a, const O: u8> ITEN_W<'a, O> {
80 #[doc = "Normal mode"]
81 #[inline(always)]
82 pub fn disabled(self) -> &'a mut W {
83 self.variant(ITEN_A::DISABLED)
84 }
85 #[doc = "The PrimeCell SSP is placed in integration test mode."]
86 #[inline(always)]
87 pub fn enabled(self) -> &'a mut W {
88 self.variant(ITEN_A::ENABLED)
89 }
90}
91#[doc = "Field `TESTFIFO` reader - Test FIFO enable"]
92pub type TESTFIFO_R = crate::BitReader<TESTFIFO_A>;
93#[doc = "Test FIFO enable\n\nValue on reset: 0"]
94#[derive(Clone, Copy, Debug, PartialEq, Eq)]
95pub enum TESTFIFO_A {
96 #[doc = "0: Normal operation"]
97 DISABLED = 0,
98 #[doc = "1: When this bit is 1, a write to the TDR writes data into the receive FIFO, and reads from the TDR reads data out of the transmit FIFO."]
99 ENABLED = 1,
100}
101impl From<TESTFIFO_A> for bool {
102 #[inline(always)]
103 fn from(variant: TESTFIFO_A) -> Self {
104 variant as u8 != 0
105 }
106}
107impl TESTFIFO_R {
108 #[doc = "Get enumerated values variant"]
109 #[inline(always)]
110 pub fn variant(&self) -> TESTFIFO_A {
111 match self.bits {
112 false => TESTFIFO_A::DISABLED,
113 true => TESTFIFO_A::ENABLED,
114 }
115 }
116 #[doc = "Checks if the value of the field is `DISABLED`"]
117 #[inline(always)]
118 pub fn is_disabled(&self) -> bool {
119 *self == TESTFIFO_A::DISABLED
120 }
121 #[doc = "Checks if the value of the field is `ENABLED`"]
122 #[inline(always)]
123 pub fn is_enabled(&self) -> bool {
124 *self == TESTFIFO_A::ENABLED
125 }
126}
127#[doc = "Field `TESTFIFO` writer - Test FIFO enable"]
128pub type TESTFIFO_W<'a, const O: u8> = crate::BitWriter<'a, u32, TCR_SPEC, TESTFIFO_A, O>;
129impl<'a, const O: u8> TESTFIFO_W<'a, O> {
130 #[doc = "Normal operation"]
131 #[inline(always)]
132 pub fn disabled(self) -> &'a mut W {
133 self.variant(TESTFIFO_A::DISABLED)
134 }
135 #[doc = "When this bit is 1, a write to the TDR writes data into the receive FIFO, and reads from the TDR reads data out of the transmit FIFO."]
136 #[inline(always)]
137 pub fn enabled(self) -> &'a mut W {
138 self.variant(TESTFIFO_A::ENABLED)
139 }
140}
141impl R {
142 #[doc = "Bit 0 - Integration test enable"]
143 #[inline(always)]
144 pub fn iten(&self) -> ITEN_R {
145 ITEN_R::new((self.bits & 1) != 0)
146 }
147 #[doc = "Bit 1 - Test FIFO enable"]
148 #[inline(always)]
149 pub fn testfifo(&self) -> TESTFIFO_R {
150 TESTFIFO_R::new(((self.bits >> 1) & 1) != 0)
151 }
152}
153impl W {
154 #[doc = "Bit 0 - Integration test enable"]
155 #[inline(always)]
156 pub fn iten(&mut self) -> ITEN_W<0> {
157 ITEN_W::new(self)
158 }
159 #[doc = "Bit 1 - Test FIFO enable"]
160 #[inline(always)]
161 pub fn testfifo(&mut self) -> TESTFIFO_W<1> {
162 TESTFIFO_W::new(self)
163 }
164 #[doc = "Writes raw bits to the register."]
165 #[inline(always)]
166 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
167 self.0.bits(bits);
168 self
169 }
170}
171#[doc = "Test control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tcr](index.html) module"]
172pub struct TCR_SPEC;
173impl crate::RegisterSpec for TCR_SPEC {
174 type Ux = u32;
175}
176#[doc = "`read()` method returns [tcr::R](R) reader structure"]
177impl crate::Readable for TCR_SPEC {
178 type Reader = R;
179}
180#[doc = "`write(|w| ..)` method takes [tcr::W](W) writer structure"]
181impl crate::Writable for TCR_SPEC {
182 type Writer = W;
183}
184#[doc = "`reset()` method sets TCR to value 0"]
185impl crate::Resettable for TCR_SPEC {
186 #[inline(always)]
187 fn reset_value() -> Self::Ux {
188 0
189 }
190}