corstone300_pac/ssp0/
dmacr.rs

1// Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
2//
3// SPDX-License-Identifier: MIT
4
5#[doc = "Register `DMACR` reader"]
6pub struct R(crate::R<DMACR_SPEC>);
7impl core::ops::Deref for R {
8    type Target = crate::R<DMACR_SPEC>;
9    #[inline(always)]
10    fn deref(&self) -> &Self::Target {
11        &self.0
12    }
13}
14impl From<crate::R<DMACR_SPEC>> for R {
15    #[inline(always)]
16    fn from(reader: crate::R<DMACR_SPEC>) -> Self {
17        R(reader)
18    }
19}
20#[doc = "Register `DMACR` writer"]
21pub struct W(crate::W<DMACR_SPEC>);
22impl core::ops::Deref for W {
23    type Target = crate::W<DMACR_SPEC>;
24    #[inline(always)]
25    fn deref(&self) -> &Self::Target {
26        &self.0
27    }
28}
29impl core::ops::DerefMut for W {
30    #[inline(always)]
31    fn deref_mut(&mut self) -> &mut Self::Target {
32        &mut self.0
33    }
34}
35impl From<crate::W<DMACR_SPEC>> for W {
36    #[inline(always)]
37    fn from(writer: crate::W<DMACR_SPEC>) -> Self {
38        W(writer)
39    }
40}
41#[doc = "Field `RXDMAE` reader - Receive DMA Enable"]
42pub type RXDMAE_R = crate::BitReader<bool>;
43#[doc = "Field `RXDMAE` writer - Receive DMA Enable"]
44pub type RXDMAE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMACR_SPEC, bool, O>;
45#[doc = "Field `TXDMAE` reader - Transmit DMA Enable"]
46pub type TXDMAE_R = crate::BitReader<bool>;
47#[doc = "Field `TXDMAE` writer - Transmit DMA Enable"]
48pub type TXDMAE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMACR_SPEC, bool, O>;
49impl R {
50    #[doc = "Bit 0 - Receive DMA Enable"]
51    #[inline(always)]
52    pub fn rxdmae(&self) -> RXDMAE_R {
53        RXDMAE_R::new((self.bits & 1) != 0)
54    }
55    #[doc = "Bit 1 - Transmit DMA Enable"]
56    #[inline(always)]
57    pub fn txdmae(&self) -> TXDMAE_R {
58        TXDMAE_R::new(((self.bits >> 1) & 1) != 0)
59    }
60}
61impl W {
62    #[doc = "Bit 0 - Receive DMA Enable"]
63    #[inline(always)]
64    pub fn rxdmae(&mut self) -> RXDMAE_W<0> {
65        RXDMAE_W::new(self)
66    }
67    #[doc = "Bit 1 - Transmit DMA Enable"]
68    #[inline(always)]
69    pub fn txdmae(&mut self) -> TXDMAE_W<1> {
70        TXDMAE_W::new(self)
71    }
72    #[doc = "Writes raw bits to the register."]
73    #[inline(always)]
74    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
75        self.0.bits(bits);
76        self
77    }
78}
79#[doc = "DMA control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dmacr](index.html) module"]
80pub struct DMACR_SPEC;
81impl crate::RegisterSpec for DMACR_SPEC {
82    type Ux = u32;
83}
84#[doc = "`read()` method returns [dmacr::R](R) reader structure"]
85impl crate::Readable for DMACR_SPEC {
86    type Reader = R;
87}
88#[doc = "`write(|w| ..)` method takes [dmacr::W](W) writer structure"]
89impl crate::Writable for DMACR_SPEC {
90    type Writer = W;
91}
92#[doc = "`reset()` method sets DMACR to value 0"]
93impl crate::Resettable for DMACR_SPEC {
94    #[inline(always)]
95    fn reset_value() -> Self::Ux {
96        0
97    }
98}
corstone300_pac/ssp0/dmacr.rs

corstone300_pac/ssp0/
dmacr.rs
