corstone300_pac/ssp0/
cr1.rs

1// Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
2//
3// SPDX-License-Identifier: MIT
4
5#[doc = "Register `CR1` reader"]
6pub struct R(crate::R<CR1_SPEC>);
7impl core::ops::Deref for R {
8    type Target = crate::R<CR1_SPEC>;
9    #[inline(always)]
10    fn deref(&self) -> &Self::Target {
11        &self.0
12    }
13}
14impl From<crate::R<CR1_SPEC>> for R {
15    #[inline(always)]
16    fn from(reader: crate::R<CR1_SPEC>) -> Self {
17        R(reader)
18    }
19}
20#[doc = "Register `CR1` writer"]
21pub struct W(crate::W<CR1_SPEC>);
22impl core::ops::Deref for W {
23    type Target = crate::W<CR1_SPEC>;
24    #[inline(always)]
25    fn deref(&self) -> &Self::Target {
26        &self.0
27    }
28}
29impl core::ops::DerefMut for W {
30    #[inline(always)]
31    fn deref_mut(&mut self) -> &mut Self::Target {
32        &mut self.0
33    }
34}
35impl From<crate::W<CR1_SPEC>> for W {
36    #[inline(always)]
37    fn from(writer: crate::W<CR1_SPEC>) -> Self {
38        W(writer)
39    }
40}
41#[doc = "Field `LBM` reader - Loop back mode"]
42pub type LBM_R = crate::BitReader<LBM_A>;
43#[doc = "Loop back mode\n\nValue on reset: 0"]
44#[derive(Clone, Copy, Debug, PartialEq, Eq)]
45pub enum LBM_A {
46    #[doc = "0: Normal serial port operation enabled"]
47    NORMAL = 0,
48    #[doc = "1: Output of transmit serial shifter is connected to input of receive serial shifter internally"]
49    LOOPBACK = 1,
50}
51impl From<LBM_A> for bool {
52    #[inline(always)]
53    fn from(variant: LBM_A) -> Self {
54        variant as u8 != 0
55    }
56}
57impl LBM_R {
58    #[doc = "Get enumerated values variant"]
59    #[inline(always)]
60    pub fn variant(&self) -> LBM_A {
61        match self.bits {
62            false => LBM_A::NORMAL,
63            true => LBM_A::LOOPBACK,
64        }
65    }
66    #[doc = "Checks if the value of the field is `NORMAL`"]
67    #[inline(always)]
68    pub fn is_normal(&self) -> bool {
69        *self == LBM_A::NORMAL
70    }
71    #[doc = "Checks if the value of the field is `LOOPBACK`"]
72    #[inline(always)]
73    pub fn is_loopback(&self) -> bool {
74        *self == LBM_A::LOOPBACK
75    }
76}
77#[doc = "Field `LBM` writer - Loop back mode"]
78pub type LBM_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, LBM_A, O>;
79impl<'a, const O: u8> LBM_W<'a, O> {
80    #[doc = "Normal serial port operation enabled"]
81    #[inline(always)]
82    pub fn normal(self) -> &'a mut W {
83        self.variant(LBM_A::NORMAL)
84    }
85    #[doc = "Output of transmit serial shifter is connected to input of receive serial shifter internally"]
86    #[inline(always)]
87    pub fn loopback(self) -> &'a mut W {
88        self.variant(LBM_A::LOOPBACK)
89    }
90}
91#[doc = "Field `SSE` reader - Synchronous serial port enable"]
92pub type SSE_R = crate::BitReader<SSE_A>;
93#[doc = "Synchronous serial port enable\n\nValue on reset: 0"]
94#[derive(Clone, Copy, Debug, PartialEq, Eq)]
95pub enum SSE_A {
96    #[doc = "0: SSP operation disabled"]
97    DISABLED = 0,
98    #[doc = "1: SSP operation enabled"]
99    ENABLED = 1,
100}
101impl From<SSE_A> for bool {
102    #[inline(always)]
103    fn from(variant: SSE_A) -> Self {
104        variant as u8 != 0
105    }
106}
107impl SSE_R {
108    #[doc = "Get enumerated values variant"]
109    #[inline(always)]
110    pub fn variant(&self) -> SSE_A {
111        match self.bits {
112            false => SSE_A::DISABLED,
113            true => SSE_A::ENABLED,
114        }
115    }
116    #[doc = "Checks if the value of the field is `DISABLED`"]
117    #[inline(always)]
118    pub fn is_disabled(&self) -> bool {
119        *self == SSE_A::DISABLED
120    }
121    #[doc = "Checks if the value of the field is `ENABLED`"]
122    #[inline(always)]
123    pub fn is_enabled(&self) -> bool {
124        *self == SSE_A::ENABLED
125    }
126}
127#[doc = "Field `SSE` writer - Synchronous serial port enable"]
128pub type SSE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, SSE_A, O>;
129impl<'a, const O: u8> SSE_W<'a, O> {
130    #[doc = "SSP operation disabled"]
131    #[inline(always)]
132    pub fn disabled(self) -> &'a mut W {
133        self.variant(SSE_A::DISABLED)
134    }
135    #[doc = "SSP operation enabled"]
136    #[inline(always)]
137    pub fn enabled(self) -> &'a mut W {
138        self.variant(SSE_A::ENABLED)
139    }
140}
141#[doc = "Field `MS` reader - Master or slave mode select"]
142pub type MS_R = crate::BitReader<MS_A>;
143#[doc = "Master or slave mode select\n\nValue on reset: 0"]
144#[derive(Clone, Copy, Debug, PartialEq, Eq)]
145pub enum MS_A {
146    #[doc = "0: Device configured as master, default"]
147    MASTER = 0,
148    #[doc = "1: Device configured as slave"]
149    SLAVE = 1,
150}
151impl From<MS_A> for bool {
152    #[inline(always)]
153    fn from(variant: MS_A) -> Self {
154        variant as u8 != 0
155    }
156}
157impl MS_R {
158    #[doc = "Get enumerated values variant"]
159    #[inline(always)]
160    pub fn variant(&self) -> MS_A {
161        match self.bits {
162            false => MS_A::MASTER,
163            true => MS_A::SLAVE,
164        }
165    }
166    #[doc = "Checks if the value of the field is `MASTER`"]
167    #[inline(always)]
168    pub fn is_master(&self) -> bool {
169        *self == MS_A::MASTER
170    }
171    #[doc = "Checks if the value of the field is `SLAVE`"]
172    #[inline(always)]
173    pub fn is_slave(&self) -> bool {
174        *self == MS_A::SLAVE
175    }
176}
177#[doc = "Field `MS` writer - Master or slave mode select"]
178pub type MS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, MS_A, O>;
179impl<'a, const O: u8> MS_W<'a, O> {
180    #[doc = "Device configured as master, default"]
181    #[inline(always)]
182    pub fn master(self) -> &'a mut W {
183        self.variant(MS_A::MASTER)
184    }
185    #[doc = "Device configured as slave"]
186    #[inline(always)]
187    pub fn slave(self) -> &'a mut W {
188        self.variant(MS_A::SLAVE)
189    }
190}
191#[doc = "Field `SOD` reader - Slave-mode output disable"]
192pub type SOD_R = crate::BitReader<SOD_A>;
193#[doc = "Slave-mode output disable\n\nValue on reset: 0"]
194#[derive(Clone, Copy, Debug, PartialEq, Eq)]
195pub enum SOD_A {
196    #[doc = "0: SSP can drive the SSPTXD output in slave mode"]
197    ENABLE = 0,
198    #[doc = "1: SSP must not drive the SSPTXD output in slave mode"]
199    DISABLE = 1,
200}
201impl From<SOD_A> for bool {
202    #[inline(always)]
203    fn from(variant: SOD_A) -> Self {
204        variant as u8 != 0
205    }
206}
207impl SOD_R {
208    #[doc = "Get enumerated values variant"]
209    #[inline(always)]
210    pub fn variant(&self) -> SOD_A {
211        match self.bits {
212            false => SOD_A::ENABLE,
213            true => SOD_A::DISABLE,
214        }
215    }
216    #[doc = "Checks if the value of the field is `ENABLE`"]
217    #[inline(always)]
218    pub fn is_enable(&self) -> bool {
219        *self == SOD_A::ENABLE
220    }
221    #[doc = "Checks if the value of the field is `DISABLE`"]
222    #[inline(always)]
223    pub fn is_disable(&self) -> bool {
224        *self == SOD_A::DISABLE
225    }
226}
227#[doc = "Field `SOD` writer - Slave-mode output disable"]
228pub type SOD_W<'a, const O: u8> = crate::BitWriter<'a, u32, CR1_SPEC, SOD_A, O>;
229impl<'a, const O: u8> SOD_W<'a, O> {
230    #[doc = "SSP can drive the SSPTXD output in slave mode"]
231    #[inline(always)]
232    pub fn enable(self) -> &'a mut W {
233        self.variant(SOD_A::ENABLE)
234    }
235    #[doc = "SSP must not drive the SSPTXD output in slave mode"]
236    #[inline(always)]
237    pub fn disable(self) -> &'a mut W {
238        self.variant(SOD_A::DISABLE)
239    }
240}
241impl R {
242    #[doc = "Bit 0 - Loop back mode"]
243    #[inline(always)]
244    pub fn lbm(&self) -> LBM_R {
245        LBM_R::new((self.bits & 1) != 0)
246    }
247    #[doc = "Bit 1 - Synchronous serial port enable"]
248    #[inline(always)]
249    pub fn sse(&self) -> SSE_R {
250        SSE_R::new(((self.bits >> 1) & 1) != 0)
251    }
252    #[doc = "Bit 2 - Master or slave mode select"]
253    #[inline(always)]
254    pub fn ms(&self) -> MS_R {
255        MS_R::new(((self.bits >> 2) & 1) != 0)
256    }
257    #[doc = "Bit 3 - Slave-mode output disable"]
258    #[inline(always)]
259    pub fn sod(&self) -> SOD_R {
260        SOD_R::new(((self.bits >> 3) & 1) != 0)
261    }
262}
263impl W {
264    #[doc = "Bit 0 - Loop back mode"]
265    #[inline(always)]
266    pub fn lbm(&mut self) -> LBM_W<0> {
267        LBM_W::new(self)
268    }
269    #[doc = "Bit 1 - Synchronous serial port enable"]
270    #[inline(always)]
271    pub fn sse(&mut self) -> SSE_W<1> {
272        SSE_W::new(self)
273    }
274    #[doc = "Bit 2 - Master or slave mode select"]
275    #[inline(always)]
276    pub fn ms(&mut self) -> MS_W<2> {
277        MS_W::new(self)
278    }
279    #[doc = "Bit 3 - Slave-mode output disable"]
280    #[inline(always)]
281    pub fn sod(&mut self) -> SOD_W<3> {
282        SOD_W::new(self)
283    }
284    #[doc = "Writes raw bits to the register."]
285    #[inline(always)]
286    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
287        self.0.bits(bits);
288        self
289    }
290}
291#[doc = "Control register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cr1](index.html) module"]
292pub struct CR1_SPEC;
293impl crate::RegisterSpec for CR1_SPEC {
294    type Ux = u32;
295}
296#[doc = "`read()` method returns [cr1::R](R) reader structure"]
297impl crate::Readable for CR1_SPEC {
298    type Reader = R;
299}
300#[doc = "`write(|w| ..)` method takes [cr1::W](W) writer structure"]
301impl crate::Writable for CR1_SPEC {
302    type Writer = W;
303}
304#[doc = "`reset()` method sets CR1 to value 0"]
305impl crate::Resettable for CR1_SPEC {
306    #[inline(always)]
307    fn reset_value() -> Self::Ux {
308        0
309    }
310}
corstone300_pac/ssp0/cr1.rs

corstone300_pac/ssp0/
cr1.rs
