corstone300_pac/ethernet/
int_en.rs

1// Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
2//
3// SPDX-License-Identifier: MIT
4
5#[doc = "Register `INT_EN` reader"]
6pub struct R(crate::R<INT_EN_SPEC>);
7impl core::ops::Deref for R {
8    type Target = crate::R<INT_EN_SPEC>;
9    #[inline(always)]
10    fn deref(&self) -> &Self::Target {
11        &self.0
12    }
13}
14impl From<crate::R<INT_EN_SPEC>> for R {
15    #[inline(always)]
16    fn from(reader: crate::R<INT_EN_SPEC>) -> Self {
17        R(reader)
18    }
19}
20#[doc = "Register `INT_EN` writer"]
21pub struct W(crate::W<INT_EN_SPEC>);
22impl core::ops::Deref for W {
23    type Target = crate::W<INT_EN_SPEC>;
24    #[inline(always)]
25    fn deref(&self) -> &Self::Target {
26        &self.0
27    }
28}
29impl core::ops::DerefMut for W {
30    #[inline(always)]
31    fn deref_mut(&mut self) -> &mut Self::Target {
32        &mut self.0
33    }
34}
35impl From<crate::W<INT_EN_SPEC>> for W {
36    #[inline(always)]
37    fn from(writer: crate::W<INT_EN_SPEC>) -> Self {
38        W(writer)
39    }
40}
41#[doc = "Field `GPIO0_INT_EN` reader - GPIO 0 Interrupt"]
42pub type GPIO0_INT_EN_R = crate::BitReader<bool>;
43#[doc = "Field `GPIO0_INT_EN` writer - GPIO 0 Interrupt"]
44pub type GPIO0_INT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_EN_SPEC, bool, O>;
45#[doc = "Field `GPIO1_INT_EN` reader - GPIO 1 Interrupt"]
46pub type GPIO1_INT_EN_R = crate::BitReader<bool>;
47#[doc = "Field `GPIO1_INT_EN` writer - GPIO 1 Interrupt"]
48pub type GPIO1_INT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_EN_SPEC, bool, O>;
49#[doc = "Field `GPIO2_INT_EN` reader - GPIO 2 Interrupt"]
50pub type GPIO2_INT_EN_R = crate::BitReader<bool>;
51#[doc = "Field `GPIO2_INT_EN` writer - GPIO 2 Interrupt"]
52pub type GPIO2_INT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_EN_SPEC, bool, O>;
53#[doc = "Field `RSFL_INT_EN` reader - RX Status FIFO Level Interrupt"]
54pub type RSFL_INT_EN_R = crate::BitReader<bool>;
55#[doc = "Field `RSFL_INT_EN` writer - RX Status FIFO Level Interrupt"]
56pub type RSFL_INT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_EN_SPEC, bool, O>;
57#[doc = "Field `RSFF_INT_EN` reader - RX Status FIFO Full Interrupt"]
58pub type RSFF_INT_EN_R = crate::BitReader<bool>;
59#[doc = "Field `RSFF_INT_EN` writer - RX Status FIFO Full Interrupt"]
60pub type RSFF_INT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_EN_SPEC, bool, O>;
61#[doc = "Field `RXDF_INT_EN` reader - RX Dropped Frame Interrupt Enable"]
62pub type RXDF_INT_EN_R = crate::BitReader<bool>;
63#[doc = "Field `RXDF_INT_EN` writer - RX Dropped Frame Interrupt Enable"]
64pub type RXDF_INT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_EN_SPEC, bool, O>;
65#[doc = "Field `TSFL_INT_EN` reader - TX Status FIFO Level Interrupt"]
66pub type TSFL_INT_EN_R = crate::BitReader<bool>;
67#[doc = "Field `TSFL_INT_EN` writer - TX Status FIFO Level Interrupt"]
68pub type TSFL_INT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_EN_SPEC, bool, O>;
69#[doc = "Field `TSFF_INT_EN` reader - TX Status FIFO Full Interrupt"]
70pub type TSFF_INT_EN_R = crate::BitReader<bool>;
71#[doc = "Field `TSFF_INT_EN` writer - TX Status FIFO Full Interrupt"]
72pub type TSFF_INT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_EN_SPEC, bool, O>;
73#[doc = "Field `TDFA_INT_EN` reader - TX Data FIFO Available Interrupt"]
74pub type TDFA_INT_EN_R = crate::BitReader<bool>;
75#[doc = "Field `TDFA_INT_EN` writer - TX Data FIFO Available Interrupt"]
76pub type TDFA_INT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_EN_SPEC, bool, O>;
77#[doc = "Field `TDFO_INT_EN` reader - TX Data FIFO Overrun Interrupt"]
78pub type TDFO_INT_EN_R = crate::BitReader<bool>;
79#[doc = "Field `TDFO_INT_EN` writer - TX Data FIFO Overrun Interrupt"]
80pub type TDFO_INT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_EN_SPEC, bool, O>;
81#[doc = "Field `TXE_INT_EN` reader - Transmitter Error Interrupt"]
82pub type TXE_INT_EN_R = crate::BitReader<bool>;
83#[doc = "Field `TXE_INT_EN` writer - Transmitter Error Interrupt"]
84pub type TXE_INT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_EN_SPEC, bool, O>;
85#[doc = "Field `RXE_INT_EN` reader - Receiver Error Interrupt"]
86pub type RXE_INT_EN_R = crate::BitReader<bool>;
87#[doc = "Field `RXE_INT_EN` writer - Receiver Error Interrupt"]
88pub type RXE_INT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_EN_SPEC, bool, O>;
89#[doc = "Field `RWT_INT_EN` reader - Receive Watchdog Time-out Interrupt"]
90pub type RWT_INT_EN_R = crate::BitReader<bool>;
91#[doc = "Field `RWT_INT_EN` writer - Receive Watchdog Time-out Interrupt"]
92pub type RWT_INT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_EN_SPEC, bool, O>;
93#[doc = "Field `TXSO_EN` reader - TX Status FIFO Overflow"]
94pub type TXSO_EN_R = crate::BitReader<bool>;
95#[doc = "Field `TXSO_EN` writer - TX Status FIFO Overflow"]
96pub type TXSO_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_EN_SPEC, bool, O>;
97#[doc = "Field `PME_INT_EN` reader - Power Management Event Interrupt Enable"]
98pub type PME_INT_EN_R = crate::BitReader<bool>;
99#[doc = "Field `PME_INT_EN` writer - Power Management Event Interrupt Enable"]
100pub type PME_INT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_EN_SPEC, bool, O>;
101#[doc = "Field `PHY_INT_EN` reader - PHY"]
102pub type PHY_INT_EN_R = crate::BitReader<bool>;
103#[doc = "Field `PHY_INT_EN` writer - PHY"]
104pub type PHY_INT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_EN_SPEC, bool, O>;
105#[doc = "Field `GPT_INT_EN` reader - GP Timer"]
106pub type GPT_INT_EN_R = crate::BitReader<bool>;
107#[doc = "Field `GPT_INT_EN` writer - GP Timer"]
108pub type GPT_INT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_EN_SPEC, bool, O>;
109#[doc = "Field `RXD_INT` reader - RX DMA Interrupt"]
110pub type RXD_INT_R = crate::BitReader<bool>;
111#[doc = "Field `RXD_INT` writer - RX DMA Interrupt"]
112pub type RXD_INT_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_EN_SPEC, bool, O>;
113#[doc = "Field `TIOC_INT_EN` reader - TX IOC Interrupt Enable"]
114pub type TIOC_INT_EN_R = crate::BitReader<bool>;
115#[doc = "Field `TIOC_INT_EN` writer - TX IOC Interrupt Enable"]
116pub type TIOC_INT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_EN_SPEC, bool, O>;
117#[doc = "Field `RXDFH_INT_EN` reader - RX Dropped Frame Counter Halfway Interrupt Enable"]
118pub type RXDFH_INT_EN_R = crate::BitReader<bool>;
119#[doc = "Field `RXDFH_INT_EN` writer - RX Dropped Frame Counter Halfway Interrupt Enable"]
120pub type RXDFH_INT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_EN_SPEC, bool, O>;
121#[doc = "Field `RXSTOP_INT_EN` reader - RX Stopped Interrupt Enable"]
122pub type RXSTOP_INT_EN_R = crate::BitReader<bool>;
123#[doc = "Field `RXSTOP_INT_EN` writer - RX Stopped Interrupt Enable"]
124pub type RXSTOP_INT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_EN_SPEC, bool, O>;
125#[doc = "Field `TXSTOP_INT_EN` reader - TX Stopped Interrupt Enable"]
126pub type TXSTOP_INT_EN_R = crate::BitReader<bool>;
127#[doc = "Field `TXSTOP_INT_EN` writer - TX Stopped Interrupt Enable"]
128pub type TXSTOP_INT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_EN_SPEC, bool, O>;
129#[doc = "Field `SW_INT_EN` reader - Software Interrupt"]
130pub type SW_INT_EN_R = crate::BitReader<bool>;
131#[doc = "Field `SW_INT_EN` writer - Software Interrupt"]
132pub type SW_INT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_EN_SPEC, bool, O>;
133impl R {
134    #[doc = "Bit 0 - GPIO 0 Interrupt"]
135    #[inline(always)]
136    pub fn gpio0_int_en(&self) -> GPIO0_INT_EN_R {
137        GPIO0_INT_EN_R::new((self.bits & 1) != 0)
138    }
139    #[doc = "Bit 1 - GPIO 1 Interrupt"]
140    #[inline(always)]
141    pub fn gpio1_int_en(&self) -> GPIO1_INT_EN_R {
142        GPIO1_INT_EN_R::new(((self.bits >> 1) & 1) != 0)
143    }
144    #[doc = "Bit 2 - GPIO 2 Interrupt"]
145    #[inline(always)]
146    pub fn gpio2_int_en(&self) -> GPIO2_INT_EN_R {
147        GPIO2_INT_EN_R::new(((self.bits >> 2) & 1) != 0)
148    }
149    #[doc = "Bit 3 - RX Status FIFO Level Interrupt"]
150    #[inline(always)]
151    pub fn rsfl_int_en(&self) -> RSFL_INT_EN_R {
152        RSFL_INT_EN_R::new(((self.bits >> 3) & 1) != 0)
153    }
154    #[doc = "Bit 4 - RX Status FIFO Full Interrupt"]
155    #[inline(always)]
156    pub fn rsff_int_en(&self) -> RSFF_INT_EN_R {
157        RSFF_INT_EN_R::new(((self.bits >> 4) & 1) != 0)
158    }
159    #[doc = "Bit 6 - RX Dropped Frame Interrupt Enable"]
160    #[inline(always)]
161    pub fn rxdf_int_en(&self) -> RXDF_INT_EN_R {
162        RXDF_INT_EN_R::new(((self.bits >> 6) & 1) != 0)
163    }
164    #[doc = "Bit 7 - TX Status FIFO Level Interrupt"]
165    #[inline(always)]
166    pub fn tsfl_int_en(&self) -> TSFL_INT_EN_R {
167        TSFL_INT_EN_R::new(((self.bits >> 7) & 1) != 0)
168    }
169    #[doc = "Bit 8 - TX Status FIFO Full Interrupt"]
170    #[inline(always)]
171    pub fn tsff_int_en(&self) -> TSFF_INT_EN_R {
172        TSFF_INT_EN_R::new(((self.bits >> 8) & 1) != 0)
173    }
174    #[doc = "Bit 9 - TX Data FIFO Available Interrupt"]
175    #[inline(always)]
176    pub fn tdfa_int_en(&self) -> TDFA_INT_EN_R {
177        TDFA_INT_EN_R::new(((self.bits >> 9) & 1) != 0)
178    }
179    #[doc = "Bit 10 - TX Data FIFO Overrun Interrupt"]
180    #[inline(always)]
181    pub fn tdfo_int_en(&self) -> TDFO_INT_EN_R {
182        TDFO_INT_EN_R::new(((self.bits >> 10) & 1) != 0)
183    }
184    #[doc = "Bit 13 - Transmitter Error Interrupt"]
185    #[inline(always)]
186    pub fn txe_int_en(&self) -> TXE_INT_EN_R {
187        TXE_INT_EN_R::new(((self.bits >> 13) & 1) != 0)
188    }
189    #[doc = "Bit 14 - Receiver Error Interrupt"]
190    #[inline(always)]
191    pub fn rxe_int_en(&self) -> RXE_INT_EN_R {
192        RXE_INT_EN_R::new(((self.bits >> 14) & 1) != 0)
193    }
194    #[doc = "Bit 15 - Receive Watchdog Time-out Interrupt"]
195    #[inline(always)]
196    pub fn rwt_int_en(&self) -> RWT_INT_EN_R {
197        RWT_INT_EN_R::new(((self.bits >> 15) & 1) != 0)
198    }
199    #[doc = "Bit 16 - TX Status FIFO Overflow"]
200    #[inline(always)]
201    pub fn txso_en(&self) -> TXSO_EN_R {
202        TXSO_EN_R::new(((self.bits >> 16) & 1) != 0)
203    }
204    #[doc = "Bit 17 - Power Management Event Interrupt Enable"]
205    #[inline(always)]
206    pub fn pme_int_en(&self) -> PME_INT_EN_R {
207        PME_INT_EN_R::new(((self.bits >> 17) & 1) != 0)
208    }
209    #[doc = "Bit 18 - PHY"]
210    #[inline(always)]
211    pub fn phy_int_en(&self) -> PHY_INT_EN_R {
212        PHY_INT_EN_R::new(((self.bits >> 18) & 1) != 0)
213    }
214    #[doc = "Bit 19 - GP Timer"]
215    #[inline(always)]
216    pub fn gpt_int_en(&self) -> GPT_INT_EN_R {
217        GPT_INT_EN_R::new(((self.bits >> 19) & 1) != 0)
218    }
219    #[doc = "Bit 20 - RX DMA Interrupt"]
220    #[inline(always)]
221    pub fn rxd_int(&self) -> RXD_INT_R {
222        RXD_INT_R::new(((self.bits >> 20) & 1) != 0)
223    }
224    #[doc = "Bit 21 - TX IOC Interrupt Enable"]
225    #[inline(always)]
226    pub fn tioc_int_en(&self) -> TIOC_INT_EN_R {
227        TIOC_INT_EN_R::new(((self.bits >> 21) & 1) != 0)
228    }
229    #[doc = "Bit 23 - RX Dropped Frame Counter Halfway Interrupt Enable"]
230    #[inline(always)]
231    pub fn rxdfh_int_en(&self) -> RXDFH_INT_EN_R {
232        RXDFH_INT_EN_R::new(((self.bits >> 23) & 1) != 0)
233    }
234    #[doc = "Bit 24 - RX Stopped Interrupt Enable"]
235    #[inline(always)]
236    pub fn rxstop_int_en(&self) -> RXSTOP_INT_EN_R {
237        RXSTOP_INT_EN_R::new(((self.bits >> 24) & 1) != 0)
238    }
239    #[doc = "Bit 25 - TX Stopped Interrupt Enable"]
240    #[inline(always)]
241    pub fn txstop_int_en(&self) -> TXSTOP_INT_EN_R {
242        TXSTOP_INT_EN_R::new(((self.bits >> 25) & 1) != 0)
243    }
244    #[doc = "Bit 31 - Software Interrupt"]
245    #[inline(always)]
246    pub fn sw_int_en(&self) -> SW_INT_EN_R {
247        SW_INT_EN_R::new(((self.bits >> 31) & 1) != 0)
248    }
249}
250impl W {
251    #[doc = "Bit 0 - GPIO 0 Interrupt"]
252    #[inline(always)]
253    pub fn gpio0_int_en(&mut self) -> GPIO0_INT_EN_W<0> {
254        GPIO0_INT_EN_W::new(self)
255    }
256    #[doc = "Bit 1 - GPIO 1 Interrupt"]
257    #[inline(always)]
258    pub fn gpio1_int_en(&mut self) -> GPIO1_INT_EN_W<1> {
259        GPIO1_INT_EN_W::new(self)
260    }
261    #[doc = "Bit 2 - GPIO 2 Interrupt"]
262    #[inline(always)]
263    pub fn gpio2_int_en(&mut self) -> GPIO2_INT_EN_W<2> {
264        GPIO2_INT_EN_W::new(self)
265    }
266    #[doc = "Bit 3 - RX Status FIFO Level Interrupt"]
267    #[inline(always)]
268    pub fn rsfl_int_en(&mut self) -> RSFL_INT_EN_W<3> {
269        RSFL_INT_EN_W::new(self)
270    }
271    #[doc = "Bit 4 - RX Status FIFO Full Interrupt"]
272    #[inline(always)]
273    pub fn rsff_int_en(&mut self) -> RSFF_INT_EN_W<4> {
274        RSFF_INT_EN_W::new(self)
275    }
276    #[doc = "Bit 6 - RX Dropped Frame Interrupt Enable"]
277    #[inline(always)]
278    pub fn rxdf_int_en(&mut self) -> RXDF_INT_EN_W<6> {
279        RXDF_INT_EN_W::new(self)
280    }
281    #[doc = "Bit 7 - TX Status FIFO Level Interrupt"]
282    #[inline(always)]
283    pub fn tsfl_int_en(&mut self) -> TSFL_INT_EN_W<7> {
284        TSFL_INT_EN_W::new(self)
285    }
286    #[doc = "Bit 8 - TX Status FIFO Full Interrupt"]
287    #[inline(always)]
288    pub fn tsff_int_en(&mut self) -> TSFF_INT_EN_W<8> {
289        TSFF_INT_EN_W::new(self)
290    }
291    #[doc = "Bit 9 - TX Data FIFO Available Interrupt"]
292    #[inline(always)]
293    pub fn tdfa_int_en(&mut self) -> TDFA_INT_EN_W<9> {
294        TDFA_INT_EN_W::new(self)
295    }
296    #[doc = "Bit 10 - TX Data FIFO Overrun Interrupt"]
297    #[inline(always)]
298    pub fn tdfo_int_en(&mut self) -> TDFO_INT_EN_W<10> {
299        TDFO_INT_EN_W::new(self)
300    }
301    #[doc = "Bit 13 - Transmitter Error Interrupt"]
302    #[inline(always)]
303    pub fn txe_int_en(&mut self) -> TXE_INT_EN_W<13> {
304        TXE_INT_EN_W::new(self)
305    }
306    #[doc = "Bit 14 - Receiver Error Interrupt"]
307    #[inline(always)]
308    pub fn rxe_int_en(&mut self) -> RXE_INT_EN_W<14> {
309        RXE_INT_EN_W::new(self)
310    }
311    #[doc = "Bit 15 - Receive Watchdog Time-out Interrupt"]
312    #[inline(always)]
313    pub fn rwt_int_en(&mut self) -> RWT_INT_EN_W<15> {
314        RWT_INT_EN_W::new(self)
315    }
316    #[doc = "Bit 16 - TX Status FIFO Overflow"]
317    #[inline(always)]
318    pub fn txso_en(&mut self) -> TXSO_EN_W<16> {
319        TXSO_EN_W::new(self)
320    }
321    #[doc = "Bit 17 - Power Management Event Interrupt Enable"]
322    #[inline(always)]
323    pub fn pme_int_en(&mut self) -> PME_INT_EN_W<17> {
324        PME_INT_EN_W::new(self)
325    }
326    #[doc = "Bit 18 - PHY"]
327    #[inline(always)]
328    pub fn phy_int_en(&mut self) -> PHY_INT_EN_W<18> {
329        PHY_INT_EN_W::new(self)
330    }
331    #[doc = "Bit 19 - GP Timer"]
332    #[inline(always)]
333    pub fn gpt_int_en(&mut self) -> GPT_INT_EN_W<19> {
334        GPT_INT_EN_W::new(self)
335    }
336    #[doc = "Bit 20 - RX DMA Interrupt"]
337    #[inline(always)]
338    pub fn rxd_int(&mut self) -> RXD_INT_W<20> {
339        RXD_INT_W::new(self)
340    }
341    #[doc = "Bit 21 - TX IOC Interrupt Enable"]
342    #[inline(always)]
343    pub fn tioc_int_en(&mut self) -> TIOC_INT_EN_W<21> {
344        TIOC_INT_EN_W::new(self)
345    }
346    #[doc = "Bit 23 - RX Dropped Frame Counter Halfway Interrupt Enable"]
347    #[inline(always)]
348    pub fn rxdfh_int_en(&mut self) -> RXDFH_INT_EN_W<23> {
349        RXDFH_INT_EN_W::new(self)
350    }
351    #[doc = "Bit 24 - RX Stopped Interrupt Enable"]
352    #[inline(always)]
353    pub fn rxstop_int_en(&mut self) -> RXSTOP_INT_EN_W<24> {
354        RXSTOP_INT_EN_W::new(self)
355    }
356    #[doc = "Bit 25 - TX Stopped Interrupt Enable"]
357    #[inline(always)]
358    pub fn txstop_int_en(&mut self) -> TXSTOP_INT_EN_W<25> {
359        TXSTOP_INT_EN_W::new(self)
360    }
361    #[doc = "Bit 31 - Software Interrupt"]
362    #[inline(always)]
363    pub fn sw_int_en(&mut self) -> SW_INT_EN_W<31> {
364        SW_INT_EN_W::new(self)
365    }
366    #[doc = "Writes raw bits to the register."]
367    #[inline(always)]
368    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
369        self.0.bits(bits);
370        self
371    }
372}
373#[doc = "Interrupt Enable Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [int_en](index.html) module"]
374pub struct INT_EN_SPEC;
375impl crate::RegisterSpec for INT_EN_SPEC {
376    type Ux = u32;
377}
378#[doc = "`read()` method returns [int_en::R](R) reader structure"]
379impl crate::Readable for INT_EN_SPEC {
380    type Reader = R;
381}
382#[doc = "`write(|w| ..)` method takes [int_en::W](W) writer structure"]
383impl crate::Writable for INT_EN_SPEC {
384    type Writer = W;
385}
386#[doc = "`reset()` method sets INT_EN to value 0"]
387impl crate::Resettable for INT_EN_SPEC {
388    #[inline(always)]
389    fn reset_value() -> Self::Ux {
390        0
391    }
392}
corstone300_pac/ethernet/int_en.rs

corstone300_pac/ethernet/
int_en.rs
