corstone300_pac/ethernet/
fifo_int.rs

1// Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
2//
3// SPDX-License-Identifier: MIT
4
5#[doc = "Register `FIFO_INT` reader"]
6pub struct R(crate::R<FIFO_INT_SPEC>);
7impl core::ops::Deref for R {
8    type Target = crate::R<FIFO_INT_SPEC>;
9    #[inline(always)]
10    fn deref(&self) -> &Self::Target {
11        &self.0
12    }
13}
14impl From<crate::R<FIFO_INT_SPEC>> for R {
15    #[inline(always)]
16    fn from(reader: crate::R<FIFO_INT_SPEC>) -> Self {
17        R(reader)
18    }
19}
20#[doc = "Register `FIFO_INT` writer"]
21pub struct W(crate::W<FIFO_INT_SPEC>);
22impl core::ops::Deref for W {
23    type Target = crate::W<FIFO_INT_SPEC>;
24    #[inline(always)]
25    fn deref(&self) -> &Self::Target {
26        &self.0
27    }
28}
29impl core::ops::DerefMut for W {
30    #[inline(always)]
31    fn deref_mut(&mut self) -> &mut Self::Target {
32        &mut self.0
33    }
34}
35impl From<crate::W<FIFO_INT_SPEC>> for W {
36    #[inline(always)]
37    fn from(writer: crate::W<FIFO_INT_SPEC>) -> Self {
38        W(writer)
39    }
40}
41#[doc = "Field `RSFL` reader - RX Status FIFO Level"]
42pub type RSFL_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `RSFL` writer - RX Status FIFO Level"]
44pub type RSFL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FIFO_INT_SPEC, u8, u8, 8, O>;
45#[doc = "Field `TSFL` reader - TX Status FIFO Level"]
46pub type TSFL_R = crate::FieldReader<u8, u8>;
47#[doc = "Field `TSFL` writer - TX Status FIFO Level"]
48pub type TSFL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FIFO_INT_SPEC, u8, u8, 8, O>;
49#[doc = "Field `TDFL` reader - TX Data FIFO Level"]
50pub type TDFL_R = crate::FieldReader<u8, u8>;
51#[doc = "Field `TDFL` writer - TX Data FIFO Level"]
52pub type TDFL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FIFO_INT_SPEC, u8, u8, 8, O>;
53impl R {
54    #[doc = "Bits 0:7 - RX Status FIFO Level"]
55    #[inline(always)]
56    pub fn rsfl(&self) -> RSFL_R {
57        RSFL_R::new((self.bits & 0xff) as u8)
58    }
59    #[doc = "Bits 16:23 - TX Status FIFO Level"]
60    #[inline(always)]
61    pub fn tsfl(&self) -> TSFL_R {
62        TSFL_R::new(((self.bits >> 16) & 0xff) as u8)
63    }
64    #[doc = "Bits 24:31 - TX Data FIFO Level"]
65    #[inline(always)]
66    pub fn tdfl(&self) -> TDFL_R {
67        TDFL_R::new(((self.bits >> 24) & 0xff) as u8)
68    }
69}
70impl W {
71    #[doc = "Bits 0:7 - RX Status FIFO Level"]
72    #[inline(always)]
73    pub fn rsfl(&mut self) -> RSFL_W<0> {
74        RSFL_W::new(self)
75    }
76    #[doc = "Bits 16:23 - TX Status FIFO Level"]
77    #[inline(always)]
78    pub fn tsfl(&mut self) -> TSFL_W<16> {
79        TSFL_W::new(self)
80    }
81    #[doc = "Bits 24:31 - TX Data FIFO Level"]
82    #[inline(always)]
83    pub fn tdfl(&mut self) -> TDFL_W<24> {
84        TDFL_W::new(self)
85    }
86    #[doc = "Writes raw bits to the register."]
87    #[inline(always)]
88    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
89        self.0.bits(bits);
90        self
91    }
92}
93#[doc = "FIFO Level Interrupt\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fifo_int](index.html) module"]
94pub struct FIFO_INT_SPEC;
95impl crate::RegisterSpec for FIFO_INT_SPEC {
96    type Ux = u32;
97}
98#[doc = "`read()` method returns [fifo_int::R](R) reader structure"]
99impl crate::Readable for FIFO_INT_SPEC {
100    type Reader = R;
101}
102#[doc = "`write(|w| ..)` method takes [fifo_int::W](W) writer structure"]
103impl crate::Writable for FIFO_INT_SPEC {
104    type Writer = W;
105}
106#[doc = "`reset()` method sets FIFO_INT to value 0x4800_0000"]
107impl crate::Resettable for FIFO_INT_SPEC {
108    #[inline(always)]
109    fn reset_value() -> Self::Ux {
110        0x4800_0000
111    }
112}
corstone300_pac/ethernet/fifo_int.rs

corstone300_pac/ethernet/
fifo_int.rs
