corstone300_pac/audio_i2s/
control.rs

1// Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
2//
3// SPDX-License-Identifier: MIT
4
5#[doc = "Register `CONTROL` reader"]
6pub struct R(crate::R<CONTROL_SPEC>);
7impl core::ops::Deref for R {
8    type Target = crate::R<CONTROL_SPEC>;
9    #[inline(always)]
10    fn deref(&self) -> &Self::Target {
11        &self.0
12    }
13}
14impl From<crate::R<CONTROL_SPEC>> for R {
15    #[inline(always)]
16    fn from(reader: crate::R<CONTROL_SPEC>) -> Self {
17        R(reader)
18    }
19}
20#[doc = "Register `CONTROL` writer"]
21pub struct W(crate::W<CONTROL_SPEC>);
22impl core::ops::Deref for W {
23    type Target = crate::W<CONTROL_SPEC>;
24    #[inline(always)]
25    fn deref(&self) -> &Self::Target {
26        &self.0
27    }
28}
29impl core::ops::DerefMut for W {
30    #[inline(always)]
31    fn deref_mut(&mut self) -> &mut Self::Target {
32        &mut self.0
33    }
34}
35impl From<crate::W<CONTROL_SPEC>> for W {
36    #[inline(always)]
37    fn from(writer: crate::W<CONTROL_SPEC>) -> Self {
38        W(writer)
39    }
40}
41#[doc = "Field `TxEnable` reader - Enable Transfer Buffer"]
42pub type TX_ENABLE_R = crate::BitReader<bool>;
43#[doc = "Field `TxEnable` writer - Enable Transfer Buffer"]
44pub type TX_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL_SPEC, bool, O>;
45#[doc = "Field `TxIRQEnable` reader - Enable Interrupt on Transmit Buffer"]
46pub type TX_IRQENABLE_R = crate::BitReader<bool>;
47#[doc = "Field `TxIRQEnable` writer - Enable Interrupt on Transmit Buffer"]
48pub type TX_IRQENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL_SPEC, bool, O>;
49#[doc = "Field `RxEnable` reader - Enable Receive Buffer"]
50pub type RX_ENABLE_R = crate::BitReader<bool>;
51#[doc = "Field `RxEnable` writer - Enable Receive Buffer"]
52pub type RX_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL_SPEC, bool, O>;
53#[doc = "Field `RxIRQEnable` reader - Enable Interrupt on Receive Buffer"]
54pub type RX_IRQENABLE_R = crate::BitReader<bool>;
55#[doc = "Field `RxIRQEnable` writer - Enable Interrupt on Receive Buffer"]
56pub type RX_IRQENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL_SPEC, bool, O>;
57#[doc = "Field `TxBufIRQLevel` reader - Transmit Buffer IRQ Water level"]
58pub type TX_BUF_IRQLEVEL_R = crate::FieldReader<u8, u8>;
59#[doc = "Field `TxBufIRQLevel` writer - Transmit Buffer IRQ Water level"]
60pub type TX_BUF_IRQLEVEL_W<'a, const O: u8> =
61    crate::FieldWriter<'a, u32, CONTROL_SPEC, u8, u8, 3, O>;
62#[doc = "Field `RxBufIRQLevel` reader - Receive Buffer IRQ Water level"]
63pub type RX_BUF_IRQLEVEL_R = crate::FieldReader<u8, u8>;
64#[doc = "Field `RxBufIRQLevel` writer - Receive Buffer IRQ Water level"]
65pub type RX_BUF_IRQLEVEL_W<'a, const O: u8> =
66    crate::FieldWriter<'a, u32, CONTROL_SPEC, u8, u8, 3, O>;
67#[doc = "Field `FIFOReset` reader - FIFO reset"]
68pub type FIFORESET_R = crate::BitReader<bool>;
69#[doc = "Field `FIFOReset` writer - FIFO reset"]
70pub type FIFORESET_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL_SPEC, bool, O>;
71#[doc = "Field `CodecReset` reader - Audio codec reset control"]
72pub type CODEC_RESET_R = crate::BitReader<bool>;
73#[doc = "Field `CodecReset` writer - Audio codec reset control"]
74pub type CODEC_RESET_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONTROL_SPEC, bool, O>;
75impl R {
76    #[doc = "Bit 0 - Enable Transfer Buffer"]
77    #[inline(always)]
78    pub fn tx_enable(&self) -> TX_ENABLE_R {
79        TX_ENABLE_R::new((self.bits & 1) != 0)
80    }
81    #[doc = "Bit 1 - Enable Interrupt on Transmit Buffer"]
82    #[inline(always)]
83    pub fn tx_irqenable(&self) -> TX_IRQENABLE_R {
84        TX_IRQENABLE_R::new(((self.bits >> 1) & 1) != 0)
85    }
86    #[doc = "Bit 2 - Enable Receive Buffer"]
87    #[inline(always)]
88    pub fn rx_enable(&self) -> RX_ENABLE_R {
89        RX_ENABLE_R::new(((self.bits >> 2) & 1) != 0)
90    }
91    #[doc = "Bit 3 - Enable Interrupt on Receive Buffer"]
92    #[inline(always)]
93    pub fn rx_irqenable(&self) -> RX_IRQENABLE_R {
94        RX_IRQENABLE_R::new(((self.bits >> 3) & 1) != 0)
95    }
96    #[doc = "Bits 8:10 - Transmit Buffer IRQ Water level"]
97    #[inline(always)]
98    pub fn tx_buf_irqlevel(&self) -> TX_BUF_IRQLEVEL_R {
99        TX_BUF_IRQLEVEL_R::new(((self.bits >> 8) & 7) as u8)
100    }
101    #[doc = "Bits 12:14 - Receive Buffer IRQ Water level"]
102    #[inline(always)]
103    pub fn rx_buf_irqlevel(&self) -> RX_BUF_IRQLEVEL_R {
104        RX_BUF_IRQLEVEL_R::new(((self.bits >> 12) & 7) as u8)
105    }
106    #[doc = "Bit 16 - FIFO reset"]
107    #[inline(always)]
108    pub fn fiforeset(&self) -> FIFORESET_R {
109        FIFORESET_R::new(((self.bits >> 16) & 1) != 0)
110    }
111    #[doc = "Bit 17 - Audio codec reset control"]
112    #[inline(always)]
113    pub fn codec_reset(&self) -> CODEC_RESET_R {
114        CODEC_RESET_R::new(((self.bits >> 17) & 1) != 0)
115    }
116}
117impl W {
118    #[doc = "Bit 0 - Enable Transfer Buffer"]
119    #[inline(always)]
120    pub fn tx_enable(&mut self) -> TX_ENABLE_W<0> {
121        TX_ENABLE_W::new(self)
122    }
123    #[doc = "Bit 1 - Enable Interrupt on Transmit Buffer"]
124    #[inline(always)]
125    pub fn tx_irqenable(&mut self) -> TX_IRQENABLE_W<1> {
126        TX_IRQENABLE_W::new(self)
127    }
128    #[doc = "Bit 2 - Enable Receive Buffer"]
129    #[inline(always)]
130    pub fn rx_enable(&mut self) -> RX_ENABLE_W<2> {
131        RX_ENABLE_W::new(self)
132    }
133    #[doc = "Bit 3 - Enable Interrupt on Receive Buffer"]
134    #[inline(always)]
135    pub fn rx_irqenable(&mut self) -> RX_IRQENABLE_W<3> {
136        RX_IRQENABLE_W::new(self)
137    }
138    #[doc = "Bits 8:10 - Transmit Buffer IRQ Water level"]
139    #[inline(always)]
140    pub fn tx_buf_irqlevel(&mut self) -> TX_BUF_IRQLEVEL_W<8> {
141        TX_BUF_IRQLEVEL_W::new(self)
142    }
143    #[doc = "Bits 12:14 - Receive Buffer IRQ Water level"]
144    #[inline(always)]
145    pub fn rx_buf_irqlevel(&mut self) -> RX_BUF_IRQLEVEL_W<12> {
146        RX_BUF_IRQLEVEL_W::new(self)
147    }
148    #[doc = "Bit 16 - FIFO reset"]
149    #[inline(always)]
150    pub fn fiforeset(&mut self) -> FIFORESET_W<16> {
151        FIFORESET_W::new(self)
152    }
153    #[doc = "Bit 17 - Audio codec reset control"]
154    #[inline(always)]
155    pub fn codec_reset(&mut self) -> CODEC_RESET_W<17> {
156        CODEC_RESET_W::new(self)
157    }
158    #[doc = "Writes raw bits to the register."]
159    #[inline(always)]
160    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
161        self.0.bits(bits);
162        self
163    }
164}
165#[doc = "Control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [control](index.html) module"]
166pub struct CONTROL_SPEC;
167impl crate::RegisterSpec for CONTROL_SPEC {
168    type Ux = u32;
169}
170#[doc = "`read()` method returns [control::R](R) reader structure"]
171impl crate::Readable for CONTROL_SPEC {
172    type Reader = R;
173}
174#[doc = "`write(|w| ..)` method takes [control::W](W) writer structure"]
175impl crate::Writable for CONTROL_SPEC {
176    type Writer = W;
177}
178#[doc = "`reset()` method sets CONTROL to value 0"]
179impl crate::Resettable for CONTROL_SPEC {
180    #[inline(always)]
181    fn reset_value() -> Self::Ux {
182        0
183    }
184}
corstone300_pac/audio_i2s/control.rs

corstone300_pac/audio_i2s/
control.rs
