corstone300_pac/isram0mpc/
int_set.rs

1// Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
2//
3// SPDX-License-Identifier: MIT
4
5#[doc = "Register `INT_SET` writer"]
6pub struct W(crate::W<INT_SET_SPEC>);
7impl core::ops::Deref for W {
8    type Target = crate::W<INT_SET_SPEC>;
9    #[inline(always)]
10    fn deref(&self) -> &Self::Target {
11        &self.0
12    }
13}
14impl core::ops::DerefMut for W {
15    #[inline(always)]
16    fn deref_mut(&mut self) -> &mut Self::Target {
17        &mut self.0
18    }
19}
20impl From<crate::W<INT_SET_SPEC>> for W {
21    #[inline(always)]
22    fn from(writer: crate::W<INT_SET_SPEC>) -> Self {
23        W(writer)
24    }
25}
26#[doc = "Field `mpc_irq` writer - mpc_irq set. Debug purpose only"]
27pub type MPC_IRQ_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_SET_SPEC, bool, O>;
28impl W {
29    #[doc = "Bit 0 - mpc_irq set. Debug purpose only"]
30    #[inline(always)]
31    pub fn mpc_irq(&mut self) -> MPC_IRQ_W<0> {
32        MPC_IRQ_W::new(self)
33    }
34    #[doc = "Writes raw bits to the register."]
35    #[inline(always)]
36    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
37        self.0.bits(bits);
38        self
39    }
40}
41#[doc = "Interrupt set. Debug purpose only\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [int_set](index.html) module"]
42pub struct INT_SET_SPEC;
43impl crate::RegisterSpec for INT_SET_SPEC {
44    type Ux = u32;
45}
46#[doc = "`write(|w| ..)` method takes [int_set::W](W) writer structure"]
47impl crate::Writable for INT_SET_SPEC {
48    type Writer = W;
49}
50#[doc = "`reset()` method sets INT_SET to value 0"]
51impl crate::Resettable for INT_SET_SPEC {
52    #[inline(always)]
53    fn reset_value() -> Self::Ux {
54        0
55    }
56}