corstone300_hal/lib.rs
1// Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
2//
3// SPDX-License-Identifier: MIT
4
5#![no_std]
6
7pub use corstone300_pac as pac;
8
9// UART = CMSDK UART
10// - 4x ttyUSB
11// - 2x Shield
12// SCC = Serial Communication Controller
13// - Motherboard Configuration Controller
14// SPI = PL022
15// - AD7490
16// - 2x Shield
17// I2C = SBCon
18// - lcd screen's touch interface STMPE811QTR
19// - audio codec CS42L52
20// - 2x Shield
21// - DDR4 SODIMM's EEPROM
22// RTC = PL031
23// DMA = PL081
24// GPIO = CMSDK AHB GPIO blocks
25// - shield
26// I2S
27// - to SC42L52
28//
29// USB is a Static Memory Interface to an ISP1763
30// mapped at 0x4150_0000 (NS) and 0x5150_0000 (Secure)
31//
32// On FPGA:
33// Ethernet is a Static Memory Interface to an SMSC LAN9220
34// mapped at 0x4140_0000 (NS) and 0x5140_0000 (Secure)
35//
36// On FVP:
37// Ethernet is a Static Memory Interface to an SMSC 91C111
38// mapped at 0x4140_0000 (NS) and 0x5140_0000 (Secure)
39
40use fugit::HertzU32;
41
42pub mod fpgaio;
43pub mod serial;
44pub mod shield;
45
46// Clock input to the FPGA
47pub mod ref_clock {
48 use fugit::HertzU32;
49
50 pub const REFCLK24MHZ: HertzU32 = HertzU32::MHz(24);
51 pub const ACLK: HertzU32 = HertzU32::MHz(32);
52 pub const MCLK: HertzU32 = HertzU32::MHz(50);
53 pub const GPUCLK: HertzU32 = HertzU32::MHz(32);
54 pub const AUDCLK: HertzU32 = HertzU32::MHz(32);
55 pub const HDLCDCLK: HertzU32 = HertzU32::MHz(32);
56}
57
58/// Clock source for SSE-300 and all non-APB peripherals in the design
59pub const MAIN_CLOCK: HertzU32 = HertzU32::MHz(32);
60
61/// Clock source for APB peripherals
62pub const PERIPHERAL_CLOCK: HertzU32 = HertzU32::MHz(25);
63
64pub const AUDMCLK: HertzU32 = HertzU32::kHz(12_290);
65pub const AUDSCLK: HertzU32 = HertzU32::kHz(3_070);
66pub const SDMCLK: HertzU32 = HertzU32::MHz(50);
67pub const CLK32KHZ: HertzU32 = HertzU32::kHz(32);
68pub const CLK100HZ: HertzU32 = HertzU32::Hz(100);
69pub const CLK1HZ: HertzU32 = HertzU32::Hz(1);