core_s3/
pins.rs

1/// ESP32-S3 GPIO number.
2#[cfg_attr(feature = "defmt", derive(defmt::Format))]
3#[derive(Clone, Copy, Debug, Eq, PartialEq, Ord, PartialOrd, Hash)]
4pub struct Gpio(pub u8);
5
6#[derive(Clone, Copy, Debug, Eq, PartialEq)]
7pub struct I2cBusPins {
8    pub sda: Gpio,
9    pub scl: Gpio,
10}
11
12impl I2cBusPins {
13    /// Internal CoreS3 peripheral bus: PMU, RTC, IMU, magnetometer, ALS/prox,
14    /// and AW9523B GPIO expander.
15    pub const INTERNAL: Self = Self {
16        sda: Gpio(12),
17        scl: Gpio(11),
18    };
19}
20
21#[derive(Clone, Copy, Debug, Eq, PartialEq)]
22pub struct SpiDisplayPins {
23    pub sclk: Gpio,
24    pub mosi: Gpio,
25    pub dc: Gpio,
26    pub cs: Gpio,
27    pub reset: Option<Gpio>,
28    pub backlight: Option<Gpio>,
29}
30
31impl SpiDisplayPins {
32    /// LCD SPI bus and control lines. Backlight/reset are controlled through the
33    /// board's power/GPIO-expander path on CoreS3, so direct GPIOs are absent.
34    pub const LCD: Self = Self {
35        sclk: Gpio(36),
36        mosi: Gpio(37),
37        dc: Gpio(35),
38        cs: Gpio(3),
39        reset: None,
40        backlight: None,
41    };
42}
43
44#[cfg_attr(feature = "defmt", derive(defmt::Format))]
45#[derive(Clone, Copy, Debug, Eq, PartialEq)]
46pub struct SpiSdPins {
47    pub sclk: Gpio,
48    pub mosi: Gpio,
49    pub miso: Gpio,
50    pub cs: Gpio,
51}
52
53impl SpiSdPins {
54    /// TF/microSD socket on the shared LCD SPI signal group.
55    pub const TF_CARD: Self = Self {
56        sclk: Gpio(36),
57        mosi: Gpio(37),
58        miso: Gpio(35),
59        cs: Gpio(4),
60    };
61}
62
63#[derive(Clone, Copy, Debug, Eq, PartialEq)]
64pub struct I2sAudioPins {
65    pub mclk: Gpio,
66    pub bclk: Gpio,
67    pub lrclk: Gpio,
68    pub dout: Gpio,
69    pub din: Gpio,
70}
71
72impl I2sAudioPins {
73    /// Shared I²S wiring for ES7210 microphone ADC and AW88298 speaker amp.
74    pub const CODECS: Self = Self {
75        mclk: Gpio(0),
76        bclk: Gpio(34),
77        lrclk: Gpio(33),
78        dout: Gpio(13),
79        din: Gpio(14),
80    };
81}
82
83#[derive(Clone, Copy, Debug, Eq, PartialEq)]
84pub struct CameraPins {
85    pub xclk: Gpio,
86    pub pclk: Gpio,
87    pub vsync: Gpio,
88    pub href: Gpio,
89    pub reset: Option<Gpio>,
90    pub data: [Gpio; 8],
91}
92
93impl CameraPins {
94    /// GC0308 DVP camera signal pins from M5Stack's CoreS3 user demo.
95    pub const GC0308: Self = Self {
96        xclk: Gpio(2),
97        pclk: Gpio(45),
98        vsync: Gpio(46),
99        href: Gpio(38),
100        reset: None,
101        data: [
102            Gpio(39),
103            Gpio(40),
104            Gpio(41),
105            Gpio(42),
106            Gpio(15),
107            Gpio(16),
108            Gpio(48),
109            Gpio(47),
110        ],
111    };
112}
113
114#[derive(Clone, Copy, Debug, Eq, PartialEq)]
115pub struct GrovePortPins {
116    pub pin1: Gpio,
117    pub pin2: Gpio,
118}
119
120impl GrovePortPins {
121    /// HY2.0-4P Grove port A exposed on CoreS3.
122    pub const PORT_A: Self = Self {
123        pin1: Gpio(1),
124        pin2: Gpio(2),
125    };
126}
core_s3/pins.rs

core_s3/
pins.rs
