consortium_ipc/side.rs
1// Copyright 2026 Ethan Wu
2//
3// Licensed under the Apache License, Version 2.0 (the "License");
4// you may not use this file except in compliance with the License.
5// You may obtain a copy of the License at
6//
7// http://www.apache.org/licenses/LICENSE-2.0
8//
9// Unless required by applicable law or agreed to in writing, software
10// distributed under the License is distributed on an "AS IS" BASIS,
11// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12// See the License for the specific language governing permissions and
13// limitations under the License.
14//
15// SPDX-License-Identifier: Apache-2.0
16
17//! Processor-side markers for dual- and triple-ported IPC peripherals.
18//!
19//! A doorbell peripheral exposes a separate register view per processor that
20//! it connects. [`Side`] identifies which view a driver instance drives:
21//!
22//! - [`Primary`] - the first processor (e.g. MU side A, IPCC processor 1,
23//! HSEM core C1).
24//! - [`Secondary`] - the second processor (e.g. MU side B, IPCC processor 2,
25//! HSEM core C2).
26//! - [`Tertiary`] - the third processor, where the peripheral supports one
27//! (e.g. HSEM core C3).
28//!
29//! [`Side`] is sealed: only the zero-sized markers in this module implement it.
30
31use crate::sealed::Sealed;
32
33/// A processor-side marker selecting which register view a doorbell drives.
34///
35/// Sealed against external implementations; see [`Primary`], [`Secondary`],
36/// and [`Tertiary`].
37pub trait Side: Sealed + Send + Sync + 'static {
38 /// Zero-based side index (`Primary` = 0, `Secondary` = 1, `Tertiary` = 2).
39 ///
40 /// Drivers map this onto their hardware numbering, e.g. a 1-based `PROC`
41 /// register bank is `INDEX + 1`.
42 const INDEX: u8;
43}
44
45/// The first processor side.
46pub struct Primary;
47
48/// The second processor side.
49pub struct Secondary;
50
51/// The third processor side, for peripherals that connect three processors.
52pub struct Tertiary;
53
54impl Side for Primary {
55 const INDEX: u8 = 0;
56}
57
58impl Side for Secondary {
59 const INDEX: u8 = 1;
60}
61
62impl Side for Tertiary {
63 const INDEX: u8 = 2;
64}