chip_gpio/
lib.rs

1extern crate glob;
2#[macro_use]
3extern crate lazy_static;
4extern crate sysfs_gpio;
5
6use std::fs::File;
7use std::io::BufReader;
8use std::io::prelude::*;
9
10use glob::glob;
11use sysfs_gpio::Pin;
12
13/// CHIP GPIO pins by name
14#[allow(non_camel_case_types)]
15#[derive(Eq,PartialEq,Debug,Copy,Clone)]
16pub enum ChipPin {
17    PWM0,
18    AP_EINT3,
19    TWI1_SCK,
20    TWI1_SDA,
21    TWI2_SCK,
22    TWI2_SDA,
23    LCD_D2,
24    LCD_D3,
25    LCD_D4,
26    LCD_D5,
27    LCD_D6,
28    LCD_D7,
29    LCD_D10,
30    LCD_D11,
31    LCD_D12,
32    LCD_D13,
33    LCD_D14,
34    LCD_D15,
35    LCD_D18,
36    LCD_D19,
37    LCD_D20,
38    LCD_D21,
39    LCD_D22,
40    LCD_D23,
41    LCD_CLK,
42    LCD_DE,
43    LCD_HSYNC,
44    LCD_VSYNC,
45    CSIPCK,
46    CSICK,
47    CSIHSYNC,
48    CSIVSYNC,
49    CSID0,
50    CSID1,
51    CSID2,
52    CSID3,
53    CSID4,
54    CSID5,
55    CSID6,
56    CSID7,
57    AP_EINT1,
58    UART1_TX,
59    UART1_RX,
60    XIO_P0,
61    XIO_P1,
62    XIO_P2,
63    XIO_P3,
64    XIO_P4,
65    XIO_P5,
66    XIO_P6,
67    XIO_P7,
68}
69
70lazy_static! {
71    static ref XIO_BASE: u64 = get_xio_base();
72}
73
74fn get_xio_base() -> u64 {
75    for entry in glob("/sys/class/gpio/*/*label").expect("Failed to read glob pattern") {
76        let path = entry.expect("Error listing /sys/class/gpio/*/*label");
77        let mut buf = [0; 8];
78        File::open(&path)
79            .expect("Failed to open label file")
80            .read(&mut buf)
81            .expect("Failed to read label file");
82        if &buf == b"pcf8574a" {
83            let file = File::open(&path.parent().unwrap().join("base"))
84                .expect("Failed to read base file");
85            let reader = BufReader::new(file);
86            return reader.lines()
87                .next()
88                .expect("Hit EOF reading XIO base file")
89                .expect("Error reading XIO base file")
90                .parse()
91                .expect("Error parsing content of XIO base file as u64");
92        }
93    }
94    panic!("Failed to find XIO base");
95}
96
97
98impl ChipPin {
99    pub fn get(self) -> Pin {
100        Pin::new(self.num())
101    }
102
103    pub fn num(self) -> u64 {
104        match self {
105            ChipPin::PWM0 => 34,
106            ChipPin::AP_EINT3 => 35,
107            ChipPin::TWI1_SCK => 47,
108            ChipPin::TWI1_SDA => 48,
109            ChipPin::TWI2_SCK => 49,
110            ChipPin::TWI2_SDA => 50,
111            ChipPin::LCD_D2 => 98,
112            ChipPin::LCD_D3 => 99,
113            ChipPin::LCD_D4 => 100,
114            ChipPin::LCD_D5 => 101,
115            ChipPin::LCD_D6 => 102,
116            ChipPin::LCD_D7 => 103,
117            ChipPin::LCD_D10 => 106,
118            ChipPin::LCD_D11 => 107,
119            ChipPin::LCD_D12 => 108,
120            ChipPin::LCD_D13 => 109,
121            ChipPin::LCD_D14 => 110,
122            ChipPin::LCD_D15 => 111,
123            ChipPin::LCD_D18 => 114,
124            ChipPin::LCD_D19 => 115,
125            ChipPin::LCD_D20 => 116,
126            ChipPin::LCD_D21 => 117,
127            ChipPin::LCD_D22 => 118,
128            ChipPin::LCD_D23 => 119,
129            ChipPin::LCD_CLK => 120,
130            ChipPin::LCD_DE => 121,
131            ChipPin::LCD_HSYNC => 122,
132            ChipPin::LCD_VSYNC => 123,
133            ChipPin::CSIPCK => 128,
134            ChipPin::CSICK => 129,
135            ChipPin::CSIHSYNC => 130,
136            ChipPin::CSIVSYNC => 131,
137            ChipPin::CSID0 => 132,
138            ChipPin::CSID1 => 133,
139            ChipPin::CSID2 => 134,
140            ChipPin::CSID3 => 135,
141            ChipPin::CSID4 => 136,
142            ChipPin::CSID5 => 137,
143            ChipPin::CSID6 => 138,
144            ChipPin::CSID7 => 139,
145            ChipPin::AP_EINT1 => 193,
146            ChipPin::UART1_TX => 195,
147            ChipPin::UART1_RX => 196,
148            ChipPin::XIO_P0 => *XIO_BASE,
149            ChipPin::XIO_P1 => *XIO_BASE + 1,
150            ChipPin::XIO_P2 => *XIO_BASE + 2,
151            ChipPin::XIO_P3 => *XIO_BASE + 3,
152            ChipPin::XIO_P4 => *XIO_BASE + 4,
153            ChipPin::XIO_P5 => *XIO_BASE + 5,
154            ChipPin::XIO_P6 => *XIO_BASE + 6,
155            ChipPin::XIO_P7 => *XIO_BASE + 7,
156        }
157    }
158}
chip_gpio/lib.rs

chip_gpio/
lib.rs
