Struct ch32v3::ch32v30x::rcc::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub ctlr: CTLR,
    pub cfgr0: CFGR0,
    pub intr: INTR,
    pub apb2prstr: APB2PRSTR,
    pub apb1prstr: APB1PRSTR,
    pub ahbpcenr: AHBPCENR,
    pub apb2pcenr: APB2PCENR,
    pub apb1pcenr: APB1PCENR,
    pub bdctlr: BDCTLR,
    pub rstsckr: RSTSCKR,
    pub ahbrstr: AHBRSTR,
    pub cfgr2: CFGR2,
}

Register block

Fields

ctlr: CTLR

0x00 - Clock control register

cfgr0: CFGR0

0x04 - Clock configuration register (RCC_CFGR0)

intr: INTR

0x08 - Clock interrupt register (RCC_INTR)

apb2prstr: APB2PRSTR

0x0c - APB2 peripheral reset register (RCC_APB2PRSTR)

apb1prstr: APB1PRSTR

0x10 - APB1 peripheral reset register (RCC_APB1PRSTR)

ahbpcenr: AHBPCENR

0x14 - AHB Peripheral Clock enable register (RCC_AHBPCENR)

apb2pcenr: APB2PCENR

0x18 - APB2 peripheral clock enable register (RCC_APB2PCENR)

apb1pcenr: APB1PCENR

0x1c - APB1 peripheral clock enable register (RCC_APB1PCENR)

bdctlr: BDCTLR

0x20 - Backup domain control register (RCC_BDCTLR)

rstsckr: RSTSCKR

0x24 - Control/status register (RCC_RSTSCKR)

ahbrstr: AHBRSTR

0x28 - AHB reset register (RCC_APHBRSTR)

cfgr2: CFGR2

0x2c - Clock configuration register2 (RCC_CFGR2)