Struct ch32v3::ch32v30x::dma2::exten_intfcr::EXTEN_INTFCR_SPEC
source · pub struct EXTEN_INTFCR_SPEC;
Expand description
DMA2 EXTEN interrupt flag clear register (DMA_INTFCR)used in ch32v30x_D8/D8C
This register you can read
, write_with_zero
, reset
, write
, modify
. See API.
For information about available fields see exten_intfcr module
Trait Implementations§
source§impl Readable for EXTEN_INTFCR_SPEC
impl Readable for EXTEN_INTFCR_SPEC
read()
method returns exten_intfcr::R reader structure
source§impl RegisterSpec for EXTEN_INTFCR_SPEC
impl RegisterSpec for EXTEN_INTFCR_SPEC
source§impl Resettable for EXTEN_INTFCR_SPEC
impl Resettable for EXTEN_INTFCR_SPEC
reset()
method sets EXTEN_INTFCR to value 0
source§const RESET_VALUE: Self::Ux = {transmute(0x00000000): <ch32v30x::dma2::exten_intfcr::EXTEN_INTFCR_SPEC as generic::RegisterSpec>::Ux}
const RESET_VALUE: Self::Ux = {transmute(0x00000000): <ch32v30x::dma2::exten_intfcr::EXTEN_INTFCR_SPEC as generic::RegisterSpec>::Ux}
Reset value of the register.
source§fn reset_value() -> Self::Ux
fn reset_value() -> Self::Ux
Reset value of the register.
source§impl Writable for EXTEN_INTFCR_SPEC
impl Writable for EXTEN_INTFCR_SPEC
write(|w| ..)
method takes exten_intfcr::W writer structure
source§const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = {transmute(0x00000000): <ch32v30x::dma2::exten_intfcr::EXTEN_INTFCR_SPEC as generic::RegisterSpec>::Ux}
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = {transmute(0x00000000): <ch32v30x::dma2::exten_intfcr::EXTEN_INTFCR_SPEC as generic::RegisterSpec>::Ux}
Specifies the register bits that are not changed if you pass
1
and are changed if you pass 0
source§const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = {transmute(0x00000000): <ch32v30x::dma2::exten_intfcr::EXTEN_INTFCR_SPEC as generic::RegisterSpec>::Ux}
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = {transmute(0x00000000): <ch32v30x::dma2::exten_intfcr::EXTEN_INTFCR_SPEC as generic::RegisterSpec>::Ux}
Specifies the register bits that are not changed if you pass
0
and are changed if you pass 1