Struct ch32v3::ch32v30x::dma1::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 30 fields
    pub intfr: INTFR,
    pub intfcr: INTFCR,
    pub cfgr1: CFGR1,
    pub cntr1: CNTR1,
    pub paddr1: PADDR1,
    pub maddr1: MADDR1,
    pub cfgr2: CFGR2,
    pub cntr2: CNTR2,
    pub paddr2: PADDR2,
    pub maddr2: MADDR2,
    pub cfgr3: CFGR3,
    pub cntr3: CNTR3,
    pub paddr3: PADDR3,
    pub maddr3: MADDR3,
    pub cfgr4: CFGR4,
    pub cntr4: CNTR4,
    pub paddr4: PADDR4,
    pub maddr4: MADDR4,
    pub cfgr5: CFGR5,
    pub cntr5: CNTR5,
    pub paddr5: PADDR5,
    pub maddr5: MADDR5,
    pub cfgr6: CFGR6,
    pub cntr6: CNTR6,
    pub paddr6: PADDR6,
    pub maddr6: MADDR6,
    pub cfgr7: CFGR7,
    pub cntr7: CNTR7,
    pub paddr7: PADDR7,
    pub maddr7: MADDR7,
    /* private fields */

}
Expand description

Register block

Fields§

§intfr: INTFR

0x00 - DMA interrupt status register (DMA_INTFR)

§intfcr: INTFCR

0x04 - DMA interrupt flag clear register (DMA_INTFCR)

§cfgr1: CFGR1

0x08 - DMA channel configuration register (DMA_CFGR)

§cntr1: CNTR1

0x0c - DMA channel 1 number of data register

§paddr1: PADDR1

0x10 - DMA channel 1 peripheral address register

§maddr1: MADDR1

0x14 - DMA channel 1 memory address register

§cfgr2: CFGR2

0x1c - DMA channel configuration register (DMA_CFGR)

§cntr2: CNTR2

0x20 - DMA channel 2 number of data register

§paddr2: PADDR2

0x24 - DMA channel 2 peripheral address register

§maddr2: MADDR2

0x28 - DMA channel 2 memory address register

§cfgr3: CFGR3

0x30 - DMA channel configuration register (DMA_CFGR)

§cntr3: CNTR3

0x34 - DMA channel 3 number of data register

§paddr3: PADDR3

0x38 - DMA channel 3 peripheral address register

§maddr3: MADDR3

0x3c - DMA channel 3 memory address register

§cfgr4: CFGR4

0x44 - DMA channel configuration register (DMA_CFGR)

§cntr4: CNTR4

0x48 - DMA channel 4 number of data register

§paddr4: PADDR4

0x4c - DMA channel 4 peripheral address register

§maddr4: MADDR4

0x50 - DMA channel 4 memory address register

§cfgr5: CFGR5

0x58 - DMA channel configuration register (DMA_CFGR)

§cntr5: CNTR5

0x5c - DMA channel 5 number of data register

§paddr5: PADDR5

0x60 - DMA channel 5 peripheral address register

§maddr5: MADDR5

0x64 - DMA channel 5 memory address register

§cfgr6: CFGR6

0x6c - DMA channel configuration register (DMA_CFGR)

§cntr6: CNTR6

0x70 - DMA channel 6 number of data register

§paddr6: PADDR6

0x74 - DMA channel 6 peripheral address register

§maddr6: MADDR6

0x78 - DMA channel 6 memory address register

§cfgr7: CFGR7

0x80 - DMA channel configuration register (DMA_CFGR)

§cntr7: CNTR7

0x84 - DMA channel 7 number of data register

§paddr7: PADDR7

0x88 - DMA channel 7 peripheral address register

§maddr7: MADDR7

0x8c - DMA channel 7 memory address register

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