Struct ch32v3::ch32v30x::adc2::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 20 fields
    pub statr: STATR,
    pub ctlr1: CTLR1,
    pub ctlr2: CTLR2,
    pub samptr1_charge1: SAMPTR1_CHARGE1,
    pub samptr2_charge2: SAMPTR2_CHARGE2,
    pub iofr1: IOFR1,
    pub iofr2: IOFR2,
    pub iofr3: IOFR3,
    pub iofr4: IOFR4,
    pub wdhtr: WDHTR,
    pub wdltr: WDLTR,
    pub rsqr1: RSQR1,
    pub rsqr2: RSQR2,
    pub rsqr3__channel: RSQR3__CHANNEL,
    pub isqr: ISQR,
    pub idatar1_chgoffset: IDATAR1_CHGOFFSET,
    pub idatar2: IDATAR2,
    pub idatar3: IDATAR3,
    pub idatar4: IDATAR4,
    pub rdatar_dr_act_dcg: RDATAR_DR_ACT_DCG,

}
Expand description

Register block

Fields§

§statr: STATR

0x00 - status register

§ctlr1: CTLR1

0x04 - control register 1/TKEY_V_CTLR

§ctlr2: CTLR2

0x08 - control register 2

§samptr1_charge1: SAMPTR1_CHARGE1

0x0c - sample time register 1

§samptr2_charge2: SAMPTR2_CHARGE2

0x10 - sample time register 2

§iofr1: IOFR1

0x14 - injected channel data offset register x

§iofr2: IOFR2

0x18 - injected channel data offset register x

§iofr3: IOFR3

0x1c - injected channel data offset register x

§iofr4: IOFR4

0x20 - injected channel data offset register x

§wdhtr: WDHTR

0x24 - watchdog higher threshold register

§wdltr: WDLTR

0x28 - watchdog lower threshold register

§rsqr1: RSQR1

0x2c - regular sequence register 1

§rsqr2: RSQR2

0x30 - regular sequence register 2

§rsqr3__channel: RSQR3__CHANNEL

0x34 - regular sequence register 3;TKEY_V_CHANNEL

§isqr: ISQR

0x38 - injected sequence register

§idatar1_chgoffset: IDATAR1_CHGOFFSET

0x3c - injected data register x_Charge data offset for injected channel x

§idatar2: IDATAR2

0x40 - injected data register x

§idatar3: IDATAR3

0x44 - injected data register x

§idatar4: IDATAR4

0x48 - injected data register x

§rdatar_dr_act_dcg: RDATAR_DR_ACT_DCG

0x4c - regular data register_start and discharge time register

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