Crate ch32rv_debug 

en: debug layer. Run control, breakpoints, GDB server (docs/cli.ja.md §4.4, §4.6).

Contract:

• Never modify target flash on attach (do not reproduce WCH OpenOCD’s behavior).
• Software breakpoints are memory-patched ebreak (RAM only for now); flash breakpoints need the QingKe trigger module and are a follow-up. GDB is told the truth (no hwbreak+ pretense like minichlink).
• V4F parts (V307/V317/H41x) have FPU registers missing from our RV32 arch; only integer registers are exposed for now (docs/architecture.ja.md §1.3).

ja: debug 層。実行制御・breakpoint・GDB server。契約: attach 時に flash を書き換えない、 SW breakpoint は memory patch(当面 RAM のみ)で実態どおり申告する、当面は整数レジスタのみ。

Re-exports

pub use arch::Rv32;

pub use arch::Rv32CoreRegs;

pub use arch::Rv32RegId;

pub use server::Ch32Target;

Modules

arch

en: A minimal RISC-V RV32 architecture for gdbstub: 32 integer GPRs plus the PC, all u32, in the order GDB’s riscv:rv32 core.xml expects (x0..x31, then pc). FPU/CSR registers are not exposed yet (docs/architecture.ja.md §1.3 notes V4F FPU needs a custom Arch later). ja: gdbstub 用の最小 RISC-V RV32 定義。GPR 32 本 + PC(すべて u32)を GDB の core.xml 順 (x0..x31, pc)で並べる。FPU/CSR は未対応(V4F FPU は将来の課題)。

server

en: A gdbstub Target for a CH32 RISC-V core reached over a DtmAccess transport. Supports registers, memory read/write, halt/continue/single-step, and breakpoints. A break GDB requests as software (Z0) is placed by the cheapest working mechanism, in order: a RAM ebreak memory-patch; else a hardware execute trigger when the core has a free slot (no wear); else a flash software breakpoint that rewrites the containing flash page (works on triggerless cores, at the cost of flash wear). Hardware breakpoints use the RISC-V trigger module (measured: 4 slots on QingKe V4F/CH32V307 and V4C/CH32X035, live-fire confirmed; 0 on V4B/CH32V203, V2A/CH32V003, V3/CH32V103 - detected dynamically). Flash software breakpoints need a verified FLASH-controller page profile (256-byte families for now; V003/V103 are a follow-up). Attach does not modify flash; flash breakpoints are removed and pages restored on detach (docs/cli.ja.md §4.6). ja: DtmAccess 上の CH32 RISC-V core 用 gdbstub Target。register・memory R/W・ halt/continue/step・breakpoint。GDB が software(Z0)で要求した break は、動く中で最も安い 手段の順(RAM ebreak patch → 空き HW trigger〔摩耗なし〕→ flash page 書き換えの flash SW breakpoint〔trigger 無し core でも効くが flash 摩耗あり〕)で張る。hardware breakpoint は RISC-V trigger module(実測: V4F/V307・V4C/X035 は 4 slot 実発火、V4B/V203・V2A/V003・V3/V103 は 0。動的検出)。flash SW breakpoint は検証済み FLASH-controller profile が必要(現状 256byte family、V003/V103 は後続)。attach で flash を書き換えず、flash breakpoint は detach 時に外して page を復元する。