Module arch 

en: A minimal RISC-V RV32 architecture for gdbstub: 32 integer GPRs plus the PC, all u32, in the order GDB’s riscv:rv32 core.xml expects (x0..x31, then pc). FPU/CSR registers are not exposed yet (docs/architecture.ja.md §1.3 notes V4F FPU needs a custom Arch later). ja: gdbstub 用の最小 RISC-V RV32 定義。GPR 32 本 + PC(すべて u32)を GDB の core.xml 順 (x0..x31, pc)で並べる。FPU/CSR は未対応(V4F FPU は将来の課題)。

Structs

Rv32CoreRegs

RV32 core register file: x0..x31 and pc.

Enums

Rv32

The RV32 architecture marker for gdbstub (zero-variant, used at the type level only).

Rv32RegId

Register identifier: a GPR index 0..31, or the PC (id 32).

Constants

RV32E_TARGET_XML

en: The target description of an RV32E hart: x0..x15 and pc (remote number 32, as GDB numbers the RISC-V pc), so GDB expects 17 registers whether or not it has the ELF. ja: RV32E の hart の target description。x0..x15 と pc(GDB の RISC-V の pc の番号 32)。ELF の 有無にかかわらず GDB は 17 本と見る。