cge_nes/ppu/registers/
mod.rs

1//! PPU register types and submodules.
2//!
3//! Contains definitions for PPU register flags, the `Register` enum, and
4//! submodules implementing register behavior and VRAM address handling.
5use crate::ppu::registers::ppu_control::PpuControlFlags;
6use crate::ppu::registers::ppu_mask::PpuMaskFlags;
7use crate::ppu::registers::ppu_status::PpuStatus;
8use ringbuffer::ConstGenericRingBuffer;
9
10mod ppu_control;
11mod ppu_mask;
12mod ppu_status;
13mod registers_impl;
14mod vram_addr;
15
16/// Enum representing the PPU's memory-mapped registers.
17///
18/// Each variant corresponds to a specific PPU register address.
19/// Used for register selection and decoding.
20#[derive(Clone, Copy, PartialEq, Eq)]
21pub enum Register {
22    /// PPU Control Register ($2000)
23    PpuControl,
24    /// PPU Mask Register ($2001)
25    PpuMask,
26    /// PPU Status Register ($2002)
27    PpuStatus,
28    /// OAM Address Register ($2003)
29    OamAddr,
30    /// OAM Data Register ($2004)
31    OamData,
32    /// PPU Scroll Register ($2005)
33    PpuScroll,
34    /// PPU Address Register ($2006)
35    PpuAddr,
36    /// PPU Data Register ($2007)
37    Data,
38}
39
40impl From<u16> for Register {
41    fn from(value: u16) -> Self {
42        match value & 0b_0111 {
43            0 => Register::PpuControl,
44            1 => Register::PpuMask,
45            2 => Register::PpuStatus,
46            3 => Register::OamAddr,
47            4 => Register::OamData,
48            5 => Register::PpuScroll,
49            6 => Register::PpuAddr,
50            7 => Register::Data,
51            _ => unreachable!(),
52        }
53    }
54}
55
56/// Holds the state of all PPU registers.
57///
58/// This struct contains the decoded values of the PPU's control, mask, status,
59/// and data registers, as well as internal latches and write toggles.
60#[derive(Clone, PartialEq, Eq)]
61pub struct Registers {
62    /// PPU Control Register flags.
63    ppu_ctrl: PpuControlFlags,
64    /// PPU Mask Register flags.
65    ppu_mask: PpuMaskFlags,
66    /// PPU Status Register flags.
67    ppu_status: PpuStatus,
68    /// OAM Address Register value.
69    oam_addr: u8,
70    /// OAM Data Register value.
71    oam_data: u8,
72    /// PPU Data Register value.
73    data: u8,
74    /// Current VRAM address (15-bit).
75    v: u16,
76    /// Temporary VRAM address (15-bit).
77    t: u16,
78    /// Fine x scroll value (3 bits)
79    x: u8,
80
81    /// Buffer to simulate the delay between toggling bg render
82    show_bg_buffer: ConstGenericRingBuffer<bool, 4>,
83    /// Buffer to simulate the delay between toggling sprites render
84    show_sprites_buffer: ConstGenericRingBuffer<bool, 4>,
85
86    /// shared write toggle for $2005/$2006 (false=first byte, true=second byte).
87    write_second: bool,
88}
cge_nes/ppu/registers/mod.rs

cge_nes/ppu/registers/
mod.rs
