Enum cfap_screen::Command

pub enum Command {
    DriverOutputControl,
    BoosterSoftStartControl,
    GateScanStartPosition,
    DeepSleepMode,
    DataEntryModeSetting,
    SwReset,
    TemperatureSensorControl,
    MasterActivation,
    DisplayUpdateControl1,
    DisplayUpdateControl2,
    WriteRam,
    WriteVcomRegister,
    WriteLutRegister,
    SetDummyLinePeriod,
    SetGateLineWidth,
    BorderWaveformControl,
    SetRamXAddressStartEndPosition,
    SetRamYAddressStartEndPosition,
    SetRamXAddressCounter,
    SetRamYAddressCounter,
    Nop,
}

Variants

DriverOutputControl

Data: A[7:0], {[0; 7], A[8]}, {[0;5], B[2:0]}

A[8:0]: MUX Sets the number of gates. MUX = A[8:0] + 1, POR = 0x12B + 1

B[2]: GD Selects first output gate. GD = 0, Selects gate sequence G0, G1, G2, G3… [POR] GD = 1, Selects gate sequence G1, G0, G3, G2…

B[1]: SM Change scanning order of gate driver. SM = 0, Selects left and ight gates interlaced: G0, G1, G2…G299. [POR] SM = 1, Selects left and right gates separated: G0, G2, G4…G298, G1, G3…G299.

B[0]: TB TB = 0, scan from G0 to G299. [POR] TB = 1, scan from G299 to G0.

BoosterSoftStartControl

Data: A[7:0], B[7:0], C[7:0]

Booster enable with Phase 1, Phase 2, and Phase 3 for soft start current settings. A[7:0]: Phase 1 A = 0x87 [POR CFAP200200A0-154] A = 0xCE [POR CFAP200200A1-154] B[7:0]: Phase 2 B = 0x86 [POR CFAP200200A0-154] B = 0xCE [POR CFAP200200A1-154] C[7:0]: Phase 3 C = 0x85 [POR CFAP200200A0-154] C = 0x8D [POR CFAP200200A1-154]

Set to A = 0xD7, B = 0xD6, and C = 0x9D in both the CFAP200200A0-154 sample code and CFAP200200A1-154 sample code.

GateScanStartPosition

Data: A[7:0], {[0; 7], A[8]}

Sets the scanning start position of the gate driver. The valid range is from 0 to 299. A = 0. [POR]

DeepSleepMode

Data: {[0; 7], A[8]}

A[0] = 0, Normal Mode [POR] A[1] = 1, Deep Sleep

DataEntryModeSetting

Data: {[0; 5], A[2:0]}

A[1:0]: ID Address automatic increment/decrement setting. ID = 0b00: Y decrement, X decrement ID = 0b01: Y decrement, X increment ID = 0b10: Y increment, X decrement ID = 0b11: Y increment, X increment [POR]

A[2]: AM Set the direction in which the address counter is updated automatically after data is written to the RAM. AM = 0, The address counter is updated in the X direction. [POR] AM = 1, The address counter is updated in the Y direction.

SwReset

Resets the commands and parameters to their POR default values except 0x10, Deep Sleep Mode. RAM is uneffected by this command.

TemperatureSensorControl

Data: A[11:4], {A[3:0], [0; 4]}

Write a 12-bit temperature value read from an external sensor.

A temperature in Celsius can be transformed into the proper value by finding the two’s complement representation of temperature multiplied by 16. A[11:0] = Temperature * 16 A = 0x7FF [POR]

Examples: Temp = 25 C, A = 400 = 0x190 Temp = -25 C, A = -400 = 0xE70

MasterActivation

Activate the Display Update Sequence. The Display Update Sequence Option is located at 0x22 (DisplayUpdateControl2). The user should not interrupt this operation to avoid corruption of panel images.

DisplayUpdateControl1

Data: {A, [0; 2], B, C[1:0], D[1:0]}

Controls the Display Update Bypass options used for Pattern Display, which is used to display the RAM content onto the display.

A: Old RAM Bypass option A = 0, Disable bypass [POR] A = 1, Enable bypass

B: Value to be used as new RAM for bypass B = 0 [POR]

C is unknown.

D[1:0]: GS Initial Update option - Source control See command 0x22 (DisplayUpdateControl2) and 0x3C (BorderWaveformControl). GS = {GSA, GSB} GS = 0b01 = {GS0, GS1} [POR]

DisplayUpdateControl2

Data: A[7:0]

Enables and disables the stages of the Display Update Sequence. The enabled stages are performed from bit 7 to bit 0.

A[7]: CLK/OSC Enable (CLKEN = 1) A[6]: CP Enable (CPEN = 1) A[5]: Load Temperature A[4]: Load LUT A[3]: Initial Display A[2]: Display Pattern A[1]: CP Disable A[0]: CLK/OSC Disable (CLKEN = 1)

Unless otherwise specified CLKEN = 0. (not specified in datasheet)

If CLKEN = 1 If CLS = VDDIO then enable OSC. If CLS = VSS then enable External Clock.

If CLKEN = 0 If CLS = VDDIO then disable OSC. If CLS = VSS then disable External Clock. (not specified in datasheet)

The author of this library has no idea what CLS refers to. It seems to be a pin that does not exist.

WriteRam

Data sent after this command is written to RAM until another command is written. Address pointer advance according to the ID setting set with command 0x11 (DataEntryModeSetting).

WriteVcomRegister

Data: A[7:0]

Write VCOM register register.

Set to 0xA8 in the CFAP200200A0-154 sample code. Set to 0x7F in the CFAP200200A1-154 sample code.

WriteLutRegister

Data: [u8; 30]

Write the LUT register.

SetDummyLinePeriod

Data: {0, A[6:0]}

Set the number of dummy line periods in terms of TGate. A = 0x16 [POR CFAP200200A0-154] A = 0x1B [POR CFAP200200A1-154] (datasheet unclear)

The author of this library does not know what TGate is.

Set to 0x1A in both the CFAP200200A0-154 sample code and CFAP200200A1-154 sample code.

SetGateLineWidth

Data: {[0; 4], A[3:0]}

Based on comments from sample code, controls the timing per line.

Set to 0x08 in the CFAP200200A0-154 sample code. Not set in the CFAP200200A1-154 sample code.

BorderWaveformControl

Data: {A, B, C[1:0], [0; 2], D[1:0]}

Selects the border waveform for the VBD.

A: Follow source at initial Update Display A = 0 [POR] A = 1, Follow source at initial Update Display for VBD. Settings B, C, and D are overridden at Initial Display stage.

B: Select GS Transition/Fix level for VBD B = 0, Select GS Transition D[3:2] for VBD. May be related to command 0x20 (DisplayUpdateControl1). B = 1, Select fix level setting C[1:0] for VBD. [POR]

C[1:0]: Fix level setting for VBD C = 0b00, VBD level is VSS. C = 0b01, VBD level is VSH. C = 0b10, VBD level is VSL. C = 0b11, VBD level is HiZ. [POR]

D[1:0]: GS transition for VBD See command 0x21 (DisplayUpdateControl1) and 0x22 (DisplayUpdateControl2). GS = {GSC, GSD} GS = 0b01 = {GS0, GS1} [POR]

SetRamXAddressStartEndPosition

Data: {[0; 3], A[4:0]}, {[0; 3], B[4:0]}

Specify the start and end positions of the window address in the X direction.

A[4:0]: XSA, X start XSA = 0x00 [POR]

B[4:0]: XEA, X end XEA = 0x18 [POR]

SetRamYAddressStartEndPosition

Data: A[7:0], {[0; 7], A[8]}, B[7:0], {[0; 7], B[8]}

Specify the start and end positions of the window address in the Y direction.

A[8:0]: YSA, Y start YSA = 0x000 [POR]

B[8:0]: YEA, Y end YEA = 0x12B [POR]

SetRamXAddressCounter

Data: {[0; 3], A[4:0]}

Initial setting for the X address counter.

A[4:0]: XAD XAD = 0x00 [POR]

SetRamYAddressCounter

Data: A[7:0], {[0; 7], A[8]}

Initial setting for the X address counter.

A[8:0]: YAD YAD = 0x000 [POR]

Nop

This command is an empty command. It does not have any effect on the display module. It can be used to terminate command 0x24 (WriteRam).

Trait Implementations

impl Clone for Command

fn clone(&self) -> Command

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Command

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Copy for Command