1use crate::HashMap;
2use crate::ir::{ModuleId, SimModule, SourceAddr, SourceVarId};
3use celox_design::RegionedAbsoluteAddrBase;
4use celox_slt::{LogicPath, SLTNodeArena};
5mod output;
6
7#[derive(Debug, Clone, PartialEq, Eq)]
13pub struct NativeProfileBlock {
14 pub function: String,
15 pub block: u32,
16 pub samples: u64,
17}
18
19#[derive(Debug, Clone, Default)]
20pub struct TraceOptions {
21 pub sim_modules: bool,
22 pub pre_atomized_comb_blocks: bool,
23 pub atomized_comb_blocks: bool,
24 pub flattened_comb_blocks: bool,
25 pub scheduled_units: bool,
26 pub pre_optimized_sir: bool,
27 pub post_optimized_sir: bool,
28 pub analyzer_ir: bool,
29 pub pre_optimized_clif: bool,
30 pub post_optimized_clif: bool,
31 pub native: bool,
32 pub mir: bool,
33 pub native_profile_blocks: Vec<NativeProfileBlock>,
34 pub output_to_stdout: bool,
35}
36
37#[derive(Debug, Clone, Default)]
38pub struct CompilationTrace {
39 pub sim_modules: Option<HashMap<ModuleId, SimModule>>,
40 pub pre_atomized_comb_blocks: Option<(Vec<LogicPath<SourceAddr>>, SLTNodeArena<SourceAddr>)>,
41 pub atomized_comb_blocks: Option<(Vec<LogicPath<SourceAddr>>, SLTNodeArena<SourceAddr>)>,
42 pub flattened_comb_blocks: Option<(Vec<LogicPath<SourceAddr>>, SLTNodeArena<SourceAddr>)>,
43 pub scheduled_units:
44 Option<Vec<celox_sir::ExecutionUnit<RegionedAbsoluteAddrBase<SourceVarId>>>>,
45 pub pre_optimized_sir: Option<crate::ir::UnoptimizedSir>,
46 pub post_optimized_sir: Option<crate::ir::OptimizedSir>,
47 pub native_optimized_sir: Option<String>,
51 pub analyzer_ir: Option<String>,
52 pub pre_optimized_clif: Option<String>,
53 pub post_optimized_clif: Option<String>,
54 pub native: Option<String>,
55 pub mir: Option<String>,
56 pub reactive_event_graph: Option<String>,
59 pub native_state_layout: Option<String>,
62}
63
64impl TraceOptions {
65 pub(crate) fn frontend(
66 &self,
67 diagnostics: &crate::RuntimeDiagnostics,
68 ) -> celox_frontend_core::FrontendTraceOptions {
69 celox_frontend_core::FrontendTraceOptions {
70 phase_timing: diagnostics.phase_timing,
71 sim_modules: self.sim_modules,
72 pre_atomized_comb_blocks: self.pre_atomized_comb_blocks,
73 atomized_comb_blocks: self.atomized_comb_blocks,
74 flattened_comb_blocks: self.flattened_comb_blocks,
75 scheduled_units: self.scheduled_units,
76 }
77 }
78}
79
80impl CompilationTrace {
81 pub(crate) fn absorb_frontend(&mut self, trace: celox_frontend_core::FrontendTrace) {
82 self.sim_modules = trace.sim_modules;
83 self.pre_atomized_comb_blocks = trace.pre_atomized_comb_blocks;
84 self.atomized_comb_blocks = trace.atomized_comb_blocks;
85 self.flattened_comb_blocks = trace.flattened_comb_blocks;
86 self.scheduled_units = trace.scheduled_units;
87 }
88}
89
90#[cfg(feature = "host-runtime")]
91pub struct CompilationTraceResult {
92 pub res: Result<crate::simulator::Simulator, crate::simulator::SimulatorError>,
93 pub trace: CompilationTrace,
94}
95
96#[cfg(feature = "host-runtime")]
97impl CompilationTraceResult {
98 pub fn expect(self, msg: &str) -> crate::simulator::Simulator {
99 match self.res {
100 Ok(sim) => sim,
101 Err(err) => {
102 self.trace.print();
103 panic!("{}: {:?}", msg, err);
104 }
105 }
106 }
107
108 pub fn unwrap(self) -> crate::simulator::Simulator {
109 match self.res {
110 Ok(sim) => sim,
111 Err(err) => {
112 self.trace.print();
113 panic!("{:?}", err);
114 }
115 }
116 }
117}