Module testbench 

Native testbench execution for Veryl #[test] modules.

Testbench expressions are compiled to a flat bytecode (TbOpcode) and evaluated by a stack-based VM that reads directly from the simulator’s memory buffer. Signals ≤64 bits use native u64 arithmetic with zero heap allocation; wider signals fall back to BigUint.

Structs

AssertionResult

Result of a single $assert evaluation.

LimitedTestbenchResult

Result of executing a testbench with an optional tick limit.

SourceLocation

TestResultDetailed

Detailed test result with assertion outcomes observed before the test finishes or stops on a fatal failure.

Enums

TestResult

Functions

compile_initial_testbench

Compile the root module’s initial block into an executable native testbench.

run_compiled_testbench

Execute a previously compiled native testbench against a built simulator.

run_compiled_testbench_with_tick_limit

Execute at most tick_limit simulator ticks from a compiled testbench.

Type Aliases

ClockCount

Clock cycle count: either a compile-time constant or a runtime expression.

CompiledTestbench

Opaque, precompiled native testbench program for a built simulator.

LoopBound