1pub mod backend;
4mod error;
5mod event_buffer;
6mod reflection;
7pub mod scheduler;
8mod simulation;
9mod testbench;
10mod vcd;
11
12pub use error::SimulatorErrorCode;
13pub use event_buffer::RuntimeEventBuffer;
14pub use reflection::{
15 DesignReflection, ReflectionScope, ReflectionScopeId, ReflectionSignal, ReflectionSignalId,
16 SignalDirection,
17};
18pub use simulation::{EventInfo, SimulationExecutor, SimulationState};
19pub use testbench::bind_testbench_program;
20pub use vcd::{VcdExternalSignalDesc, VcdSignalDesc, VcdWriter};
21
22pub type AbsoluteAddr = celox_design::StateAddr;
23pub type MemoryLayout = celox_state_layout::MemoryLayout<AbsoluteAddr>;
24
25#[derive(
26 Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, serde::Serialize, serde::Deserialize,
27)]
28pub struct SignalArrayLayout {
29 pub element_width: usize,
30 pub element_count: usize,
31 pub element_stride: usize,
32 pub plane_size: usize,
33}
34
35#[derive(
36 Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, serde::Serialize, serde::Deserialize,
37)]
38pub struct SignalRef {
39 pub offset: usize,
40 pub width: usize,
41 pub is_4state: bool,
42 pub array_layout: Option<SignalArrayLayout>,
43}