celox_frontend_core/
trace.rs

1use celox_design::ModuleId;
2use celox_sir::ExecutionUnit;
3use celox_slt::{LogicPath, SLTNodeArena};
4
5use crate::{HashMap, SourceAddr, SourceVarId, symbolic::artifact::SimModule};
6
7type RegionedSourceAddr = celox_design::RegionedAbsoluteAddrBase<SourceVarId>;
8
9/// Source-neutral symbolic module retained only when frontend tracing is enabled.
10pub type TraceSimModule = SimModule;
11
12/// Frontend-owned trace switches. Backend and optimizer trace options are
13/// intentionally absent from this contract.
14#[derive(Debug, Clone, Copy, Default)]
15pub struct FrontendTraceOptions {
16    pub phase_timing: bool,
17    pub sim_modules: bool,
18    pub pre_atomized_comb_blocks: bool,
19    pub atomized_comb_blocks: bool,
20    pub flattened_comb_blocks: bool,
21    pub scheduled_units: bool,
22}
23
24/// Optional diagnostics produced while `SymbolicRtl` is consumed.
25#[derive(Debug, Clone, Default)]
26pub struct FrontendTrace {
27    pub sim_modules: Option<HashMap<ModuleId, SimModule>>,
28    pub pre_atomized_comb_blocks: Option<(Vec<LogicPath<SourceAddr>>, SLTNodeArena<SourceAddr>)>,
29    pub atomized_comb_blocks: Option<(Vec<LogicPath<SourceAddr>>, SLTNodeArena<SourceAddr>)>,
30    pub flattened_comb_blocks: Option<(Vec<LogicPath<SourceAddr>>, SLTNodeArena<SourceAddr>)>,
31    pub scheduled_units: Option<Vec<ExecutionUnit<RegionedSourceAddr>>>,
32}
celox_frontend_core/trace.rs

celox_frontend_core/
trace.rs
