celox_backend_x86/
lib.rs

1//! Self-contained x86-64 code-generation kernel.
2//!
3//! The crate consumes source-independent SIR plus a finalized physical state
4//! layout. It does not know about the Veryl frontend, simulator facade, or
5//! testbench runtime.
6
7pub type HashMap<K, V> = fxhash::FxHashMap<K, V>;
8pub type HashSet<K> = fxhash::FxHashSet<K>;
9
10#[derive(Debug, Clone, PartialEq, Eq)]
11pub struct NativeDumpOptions {
12    pub block: usize,
13    pub label: Option<String>,
14    pub stage: Option<String>,
15    pub dump_sir: bool,
16    pub mir_limit: usize,
17}
18
19impl Default for NativeDumpOptions {
20    fn default() -> Self {
21        Self {
22            block: 0,
23            label: None,
24            stage: None,
25            dump_sir: true,
26            mir_limit: 64,
27        }
28    }
29}
30
31#[derive(Debug, Clone, Default, PartialEq, Eq)]
32pub struct NativeDiagnostics {
33    pub phase_timing: bool,
34    pub regalloc_timing: bool,
35    pub regalloc_stats: bool,
36    pub mir_stats: bool,
37    pub mir_block_stats: bool,
38    pub verify_sir: bool,
39    pub verify_mir: bool,
40    pub verify_mir_passes: bool,
41    pub verify_regalloc: bool,
42    pub isel_trace_regs: Vec<usize>,
43    pub dump: Option<NativeDumpOptions>,
44    pub perf_map: bool,
45}
46
47#[derive(Debug, Clone)]
48pub struct X86BackendOptions {
49    /// Prefer low compilation latency for the first native execution tier.
50    pub baseline: bool,
51    pub slp: bool,
52    pub native_tick_loop: bool,
53    pub diagnostics: NativeDiagnostics,
54}
55
56impl Default for X86BackendOptions {
57    fn default() -> Self {
58        Self {
59            slp: true,
60            native_tick_loop: true,
61            baseline: false,
62            diagnostics: NativeDiagnostics::default(),
63        }
64    }
65}
66
67pub use celox_design::{
68    AbsoluteAddrBase, BinaryOp, DomainKind, InstanceId, RegionedAbsoluteAddrBase, RuntimeEventKind,
69    SPARSE_WORKING_REGION, STABLE_REGION, StateAddr, TriggerIdWithKind, UnaryOp, WORKING_REGION,
70};
71pub use celox_sir::*;
72
73pub type AbsoluteAddr = celox_design::StateAddr;
74pub type RegionedAbsoluteAddr = celox_design::RegionedStateAddr;
75pub type SirProgram = celox_sir::SirProgram<AbsoluteAddr, RegionedAbsoluteAddr>;
76pub type MemoryLayout = celox_state_layout::MemoryLayout<AbsoluteAddr>;
77
78/// Remaining iterations for an in-function native tick loop.
79pub const STATE_HEADER_NATIVE_LOOP_REMAINING_OFFSET: usize = 8;
80/// Runtime-event sequence observed when a native tick batch starts.
81pub const STATE_HEADER_NATIVE_LOOP_EVENT_SEQ_OFFSET: usize = 24;
82
83const _: () = {
84    assert!(
85        celox_state_layout::STATE_HEADER_RUNTIME_EVENT_ADDR_OFFSET + 8
86            <= STATE_HEADER_NATIVE_LOOP_REMAINING_OFFSET
87    );
88    assert!(
89        STATE_HEADER_NATIVE_LOOP_REMAINING_OFFSET + 8
90            <= celox_state_layout::STATE_HEADER_COMB_CAPTURE_ENABLED_ADDR_OFFSET
91    );
92    assert!(
93        celox_state_layout::STATE_HEADER_COMB_CAPTURE_ENABLED_ADDR_OFFSET + 8
94            <= STATE_HEADER_NATIVE_LOOP_EVENT_SEQ_OFFSET
95    );
96    assert!(STATE_HEADER_NATIVE_LOOP_EVENT_SEQ_OFFSET + 8 <= celox_state_layout::STATE_HEADER_SIZE);
97};
98
99pub mod timing {
100    pub fn now() -> std::time::Instant {
101        std::time::Instant::now()
102    }
103}
104
105#[path = "backend/native/mod.rs"]
106pub mod native;
107
108pub use native::*;
celox_backend_x86/lib.rs

celox_backend_x86/
lib.rs
