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celox_backend_x86/backend/native/
mod.rs

1//! x86-64 backend pipeline: SIR → MIR → allocation → machine code.
2
3#[cfg(any(target_arch = "x86_64", feature = "cross-codegen"))]
4pub mod emit;
5#[cfg_attr(not(target_arch = "x86_64"), allow(dead_code))]
6pub mod features;
7pub mod isel;
8#[cfg(any(target_arch = "x86_64", feature = "cross-codegen"))]
9pub mod jit_mem;
10pub mod memory_effect;
11pub mod mir;
12pub mod mir_legalize;
13pub mod mir_opt;
14pub mod mir_verify;
15#[cfg_attr(not(target_arch = "x86_64"), allow(dead_code))]
16pub mod regalloc;
17pub mod scalar_pipeline;
18mod sparse_write_state;
19#[cfg_attr(not(target_arch = "x86_64"), allow(dead_code))]
20pub mod ssa_destroy;
21#[cfg_attr(not(target_arch = "x86_64"), allow(dead_code))]
22pub mod x86_slp;