cc3220sf/gprcm/
nwp_sram_dslp_cfg.rs

1#[doc = "Reader of register NWP_SRAM_DSLP_CFG"]
2pub type R = crate::R<u32, super::NWP_SRAM_DSLP_CFG>;
3#[doc = "Writer for register NWP_SRAM_DSLP_CFG"]
4pub type W = crate::W<u32, super::NWP_SRAM_DSLP_CFG>;
5#[doc = "Register NWP_SRAM_DSLP_CFG `reset()`'s with value 0"]
6impl crate::ResetValue for super::NWP_SRAM_DSLP_CFG {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `NWP_SRAM_DSLP_CFG`"]
14pub type NWP_SRAM_DSLP_CFG_R = crate::R<u32, u32>;
15#[doc = "Write proxy for field `NWP_SRAM_DSLP_CFG`"]
16pub struct NWP_SRAM_DSLP_CFG_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> NWP_SRAM_DSLP_CFG_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u32) -> &'a mut W {
23        self.w.bits = (self.w.bits & !0x000f_ffff) | ((value as u32) & 0x000f_ffff);
24        self.w
25    }
26}
27impl R {
28    #[doc = "Bits 0:19 - Configuration of NWP Memories during DSLP : 0 - SRAMs are OFF ; 1 - SRAMs are Retained. NWP SRAM Cluster information : \\[2\\]
29- 3rd column in MEMSS (Applicable only when owned by NWP) ; \\[3\\]
30- 4th column in MEMSS (Applicable only when owned by NWP) ; \\[4\\]
31- 5th column in MEMSS (Applicable only when owned by NWP) ; \\[5\\]
32- 6th column in MEMSS (Applicable only when owned by NWP) ; \\[6\\]
33- 7th column in MEMSS (Applicable only when owned by NWP) ; \\[7\\]
34- 8th column in MEMSS (Applicable only when owned by NWP) ; \\[8\\]
35- 9th column in MEMSS (Applicable only when owned by NWP) ; \\[9\\]
36- 10th column in MEMSS (Applicable only when owned by NWP) ; \\[10\\]
37- 11th column in MEMSS (Applicable only when owned by NWP) ; \\[11\\]
38- 12th column in MEMSS (Applicable only when owned by NWP) ; \\[12\\]
39- 13th column in MEMSS (Applicable only when owned by NWP) ; \\[13\\]
40- 14th column in MEMSS (Applicable only when owned by NWP) ; \\[14\\]
41- 15th column in MEMSS (Applicable only when owned by NWP) ; \\[19:18\\]
42- Reserved."]
43    #[inline(always)]
44    pub fn nwp_sram_dslp_cfg(&self) -> NWP_SRAM_DSLP_CFG_R {
45        NWP_SRAM_DSLP_CFG_R::new((self.bits & 0x000f_ffff) as u32)
46    }
47}
48impl W {
49    #[doc = "Bits 0:19 - Configuration of NWP Memories during DSLP : 0 - SRAMs are OFF ; 1 - SRAMs are Retained. NWP SRAM Cluster information : \\[2\\]
50- 3rd column in MEMSS (Applicable only when owned by NWP) ; \\[3\\]
51- 4th column in MEMSS (Applicable only when owned by NWP) ; \\[4\\]
52- 5th column in MEMSS (Applicable only when owned by NWP) ; \\[5\\]
53- 6th column in MEMSS (Applicable only when owned by NWP) ; \\[6\\]
54- 7th column in MEMSS (Applicable only when owned by NWP) ; \\[7\\]
55- 8th column in MEMSS (Applicable only when owned by NWP) ; \\[8\\]
56- 9th column in MEMSS (Applicable only when owned by NWP) ; \\[9\\]
57- 10th column in MEMSS (Applicable only when owned by NWP) ; \\[10\\]
58- 11th column in MEMSS (Applicable only when owned by NWP) ; \\[11\\]
59- 12th column in MEMSS (Applicable only when owned by NWP) ; \\[12\\]
60- 13th column in MEMSS (Applicable only when owned by NWP) ; \\[13\\]
61- 14th column in MEMSS (Applicable only when owned by NWP) ; \\[14\\]
62- 15th column in MEMSS (Applicable only when owned by NWP) ; \\[19:18\\]
63- Reserved."]
64    #[inline(always)]
65    pub fn nwp_sram_dslp_cfg(&mut self) -> NWP_SRAM_DSLP_CFG_W {
66        NWP_SRAM_DSLP_CFG_W { w: self }
67    }
68}
cc3220sf/gprcm/nwp_sram_dslp_cfg.rs

cc3220sf/gprcm/
nwp_sram_dslp_cfg.rs
