cc3220sf/ocp_shared/
cc3xx_debugmux_sel.rs

1#[doc = "Reader of register CC3XX_DEBUGMUX_SEL"]
2pub type R = crate::R<u32, super::CC3XX_DEBUGMUX_SEL>;
3#[doc = "Writer for register CC3XX_DEBUGMUX_SEL"]
4pub type W = crate::W<u32, super::CC3XX_DEBUGMUX_SEL>;
5#[doc = "Register CC3XX_DEBUGMUX_SEL `reset()`'s with value 0"]
6impl crate::ResetValue for super::CC3XX_DEBUGMUX_SEL {
7    type Type = u32;
8    #[inline(always)]
9    fn reset_value() -> Self::Type {
10        0
11    }
12}
13#[doc = "Reader of field `MEM_CC3XX_DEBUGMUX_SEL`"]
14pub type MEM_CC3XX_DEBUGMUX_SEL_R = crate::R<u16, u16>;
15#[doc = "Write proxy for field `MEM_CC3XX_DEBUGMUX_SEL`"]
16pub struct MEM_CC3XX_DEBUGMUX_SEL_W<'a> {
17    w: &'a mut W,
18}
19impl<'a> MEM_CC3XX_DEBUGMUX_SEL_W<'a> {
20    #[doc = r"Writes raw bits to the field"]
21    #[inline(always)]
22    pub unsafe fn bits(self, value: u16) -> &'a mut W {
23        self.w.bits = (self.w.bits & !0xffff) | ((value as u32) & 0xffff);
24        self.w
25    }
26}
27impl R {
28    #[doc = "Bits 0:15 - debug mux select register. Upper 8 bits are used for debug module selection. Lower 8 bit \\[7:0\\]
29used inside debug module for selecting module specific signals. Bits\\[15:8: when set x&quot;00&quot; : GPRCM debug bus. When &quot;o1&quot; : SDIO debug debug bus when x&quot;02&quot; : autonoumous SPI when x&quot;03&quot; : TOPIC when x&quot;04&quot;: memss when x&quot;25&quot;: mcu debug bus : APPS debug when x&quot;45&quot;: mcu debug bus : NWP debug when x&quot;65&quot;: mcu debug bus : AHB2VBUS debug when x&quot;85&quot;: mcu debug bus : VBUS2HAB debug when x&quot;95&quot;: mcu debug bus : RCM debug when x&quot;A5&quot;: mcu debug bus : crypto debug when x&quot;06&quot;: WLAN debug bus when x&quot;07&quot;: debugss bus when x&quot;08&quot;: ADC debug when x&quot;09&quot;: SDIO PHY debug bus then &quot;others&quot; : no debug is selected"]
30    #[inline(always)]
31    pub fn mem_cc3xx_debugmux_sel(&self) -> MEM_CC3XX_DEBUGMUX_SEL_R {
32        MEM_CC3XX_DEBUGMUX_SEL_R::new((self.bits & 0xffff) as u16)
33    }
34}
35impl W {
36    #[doc = "Bits 0:15 - debug mux select register. Upper 8 bits are used for debug module selection. Lower 8 bit \\[7:0\\]
37used inside debug module for selecting module specific signals. Bits\\[15:8: when set x&quot;00&quot; : GPRCM debug bus. When &quot;o1&quot; : SDIO debug debug bus when x&quot;02&quot; : autonoumous SPI when x&quot;03&quot; : TOPIC when x&quot;04&quot;: memss when x&quot;25&quot;: mcu debug bus : APPS debug when x&quot;45&quot;: mcu debug bus : NWP debug when x&quot;65&quot;: mcu debug bus : AHB2VBUS debug when x&quot;85&quot;: mcu debug bus : VBUS2HAB debug when x&quot;95&quot;: mcu debug bus : RCM debug when x&quot;A5&quot;: mcu debug bus : crypto debug when x&quot;06&quot;: WLAN debug bus when x&quot;07&quot;: debugss bus when x&quot;08&quot;: ADC debug when x&quot;09&quot;: SDIO PHY debug bus then &quot;others&quot; : no debug is selected"]
38    #[inline(always)]
39    pub fn mem_cc3xx_debugmux_sel(&mut self) -> MEM_CC3XX_DEBUGMUX_SEL_W {
40        MEM_CC3XX_DEBUGMUX_SEL_W { w: self }
41    }
42}
cc3220sf/ocp_shared/cc3xx_debugmux_sel.rs

cc3220sf/ocp_shared/
cc3xx_debugmux_sel.rs
