[−][src]Type Definition cc3220sf::gpioa0::DR2R
type DR2R = Reg<u32, _DR2R>;
0x4000 5500 0x4000 6500 0x4000 7500 0x4002 4500 GPIO 2-mA Drive Select (GPIODR2R)@@ offset 0x500 The GPIODR2R register is the 2-mA drive control register. Each GPIO signal in the port can be individually configured without affecting the other pads. When setting the DRV2 bit for a GPIO signal@@ the corresponding DRV4 bit in the GPIODR4R register and DRV8 bit in the GPIODR8R register are automatically cleared by hardware. By default@@ all GPIO pins have 2-mA drive.
This register you can read
, reset
, write
, write_with_zero
, modify
. See API.
For information about available fields see dr2r module