[−][src]Type Definition cc3220sf::ocp_shared::semaphore5::R
type R = R<u32, SEMAPHORE5>;
Reader of register SEMAPHORE5
Implementations
impl R
[src]
pub fn mem_semaphore5(&self) -> MEM_SEMAPHORE5_R
[src]
Bits 0:1 - General Purpose Semaphore for SW Usage. If any of the 2 bits of a given register is set to 1, it means that the semaphore is locked by one of the masters. Each bit represents a master IP as follows: {WLAN,NWP}. The JTAG cannot capture the semaphore but it can release it. As a master IP reads the semaphore, it will be caputed and the masters correlating bit will be set to 1 (set upon read). As any IP writes to this address (independent of the written data) the semaphore will be set to 2'b00.