Type Definition cc3220sf::ocp_shared::gpio_pad_config_36::R

type R = R<u32, GPIO_PAD_CONFIG_36>;

Reader of register GPIO_PAD_CONFIG_36

Implementations

impl R

pub fn mem_gpio_pad_config_36(&self) -> MEM_GPIO_PAD_CONFIG_36_R

Bits 0:5 - GPIO 0 register: "Bit 0 - 3 is used for PAD IO mode selection. io_register={ "" 0 => """"CONFMODE[0]"""""" "" 1 => """"CONFMODE[1]"""""" "" 2 => """"CONFMODE[2]"""""" "" 3 => """"CONFMODE[3]"""" 4 => """"IOE_N"""" --> output enable value. level 0 enables the IDO to PAD path. Else PAD is tristated (except for the PU/PD which are independent)." "Value gets latched at rising edge of RET33""" """ 5 =>"""" IOE_N_OV"""" --> output enable overirde. when bit is set to logic '1' IOE_N (bit 4) value will control IO IOE_N signal else IOE_N is control via selected HW logic. strong PULL UP and PULL Down control is disabled for all IO's. both controls are tied to logic level '0'. IODEN and I8MAEN is diesabled for all development IO's. These signals are tied to logic level '0'. common control is implemented for I2MAEN, I4MAEN, WKPU, WKPD control . refer dev_pad_cmn_config register bits.