Type Definition cc3220sf::ocp_shared::cc3xx_shared_mem_sel_msb::R

type R = R<u32, CC3XX_SHARED_MEM_SEL_MSB>;

Reader of register CC3XX_SHARED_MEM_SEL_MSB

Implementations

impl R

pub fn mem_shared_mem_sel_msb(&self) -> MEM_SHARED_MEM_SEL_MSB_R

Bits 0:11 - This register provides memss RAM column configuration for column 10 to 15. 3 bits are allocated per column. This register is required to be configured before starting RAM access. Changing register setting while code is running will result into unpredictable memory behaviour. Register is supported to configured ones after core is booted up. 3 bit encoding per column is as follows: when 000 : WLAN, 001: NWP, 010: APPS, 011: PHY, 100: OCLA column 11 select : bit [2:0] column 12 select : bit [5:3] column 13 select : bit [8 : 6] column 14 select :